公开(公告)号：US20240355819A1

公开(公告)日：2024-10-24

申请号：US18760970

申请日：2024-07-01

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20220262791A1

公开(公告)日：2022-08-18

申请号：US17176412

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.