公开(公告)号：US20220262791A1

公开(公告)日：2022-08-18

申请号：US17176412

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20230317731A1

公开(公告)日：2023-10-05

申请号：US17709378

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/76283

Abstract: Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.

公开(公告)号：US20200279069A1

公开(公告)日：2020-09-03

申请号：US16649588

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Ranjith KUMAR ,  Mark T. BOHR ,  Ruth A. BRAIN ,  Marni NABORS ,  Tai-Hsuan WU ,  Sourav CHAKRAVARTY

IPC: G06F30/3953 ,  H01L23/50 ,  H01L23/522

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

公开(公告)号：US20230197779A1

公开(公告)日：2023-06-22

申请号：US17556602

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Marni NABORS ,  Mauro J. KOBRINSKY ,  Conor P. PULS ,  Kevin FISCHER ,  Curtis TSAI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L23/481

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.

公开(公告)号：US20200251464A1

公开(公告)日：2020-08-06

申请号：US16263093

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Srinivasa Chaitanya GADIGATLA ,  Ranjith KUMAR ,  Marni NABORS ,  Quan PHAN

IPC: H01L27/02 ,  H01L27/118 ,  H01L23/528

Abstract: An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.

公开(公告)号：US20240355819A1

公开(公告)日：2024-10-24

申请号：US18760970

申请日：2024-07-01

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20230317787A1

公开(公告)日：2023-10-05

申请号：US17709374

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0886

Abstract: Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

公开(公告)号：US20220285342A1

公开(公告)日：2022-09-08

申请号：US17825664

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Yih WANG ,  Rishabh MEHANDRU ,  Mauro J. KOBRINSKY ,  Tahir GHANI ,  Mark BOHR ,  Marni NABORS

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.