公开(公告)号：US20240355819A1

公开(公告)日：2024-10-24

申请号：US18760970

申请日：2024-07-01

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20230317602A1

公开(公告)日：2023-10-05

申请号：US17710871

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Richard E. SCHENKER ,  Xinning WANG ,  Tahir GHANI

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L27/092

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420512A1

公开(公告)日：2023-12-28

申请号：US17850778

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Xinning WANG ,  Nischal ARKALI RADHAKRISHNA ,  Leonard P. GULER ,  Mauro J. KOBRINSKY ,  June CHOI ,  Pratik PATEL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/481 ,  H01L29/42392

Abstract: Integrated circuit structures having backside power staple are described. In an example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts is extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A front-side metal routing layer is extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts. A backside metal routing layer is extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer. A conductive feedthrough structure couples the backside metal routing layer to the front-side metal routing layer.

公开(公告)号：US20220262791A1

公开(公告)日：2022-08-18

申请号：US17176412

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Quan SHI ,  Sukru YEMENICIOGLU ,  Marni NABORS ,  Nikolay RYZHENKO ,  Xinning WANG ,  Sivakumar VENKATARAMAN

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.