公开(公告)号：US12282377B2

公开(公告)日：2025-04-22

申请号：US17358224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Pritesh P. Shah ,  Suresh Chemudupati ,  Alexander Gendler ,  David Hunt ,  Christopher M. Macnamara ,  Ofer Nathan ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3287 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/50

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.