公开(公告)号：US20220107838A1

公开(公告)日：2022-04-07

申请号：US17644117

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Bruce RICHARDSON ,  Rahul SHAH ,  Pravin PATHAK ,  Rashmi SHETTY

IPC: G06F9/48

Abstract: Examples relate to an apparatus, device, method, and computer program for processing a sequence of units of data, and of a computer program comprising such an apparatus or device. The apparatus comprises processing circuitry configured to obtain the sequence of units of data, obtain tokens indicating a readiness of a plurality of worker threads being executed on the processing circuitry, and process sub-sequences of the sequence of units of data by selecting, by a queue management circuitry of the processing circuitry, a worker thread from the plurality of worker threads based on the obtained tokens indicating the readiness, providing, by the queue management circuitry, a lock to a queue associated with the worker thread, the lock being associated with a resource comprising a sub-sequence of the sequence of units of data, obtaining, by the queue management circuitry, the lock from the worker thread after the worker thread has at least partially processed the sub-sequence of units of data stored in the resource, and proceeding with the next sub-sequence after the lock has been obtained.

公开(公告)号：US20230198912A1

公开(公告)日：2023-06-22

申请号：US17553543

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Pravin PATHAK ,  Rahul SHAH ,  Declan DOHERTY

IPC: H04L47/34 ,  H04L47/2441 ,  H04L47/27

CPC classification number: H04L47/34 ,  H04L47/2441 ,  H04L47/27 ,  H04L63/18

Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.

公开(公告)号：US20240281375A1

公开(公告)日：2024-08-22

申请号：US18651039

申请日：2024-04-30

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Yi ZENG ,  Rahul SHAH ,  Krzysztof WOJCIK

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F2212/16

Abstract: Examples described herein relate to communications with a bootable processor. Some examples include allocating memory address space to provide access to communications over general purpose input output (GPIO)-consistent pins, wherein the GPIO-consistent pins comprise pins coupled to the bootable processor and a pin of the pins coupled to the bootable processor receives or transmits communication for multiple platform GPIO pins.