公开(公告)号：US20220383941A1

公开(公告)日：2022-12-01

申请号：US17818553

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Rakan Maddah ,  Mu Lim Edwin Cheng ,  Bei Wang ,  Prashant S. Damle

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Systems, apparatuses and methods may provide for technology that determines a power-off period associated with a non-volatile memory (NVM), sets a completion time of a write procedure corresponding to the NVM to a first value if the power-off period exceeds a threshold, and sets the completion time to a second value if the power-off period does not exceed the threshold, wherein the first value is greater than the second value.

公开(公告)号：US20220382465A1

公开(公告)日：2022-12-01

申请号：US17818161

申请日：2022-08-08

Applicant: Intel Corporation

Inventor： Rakan Maddah ,  Jason Gayman ,  Arjun Kripanidhi ,  Wilson Fang ,  Prashant S. Damle

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that determines a write-to-write delay with respect to a memory cell, wherein one or more neighboring cells are adjacent to the memory cell and controls a write disturb refresh rate of the one or more neighboring cells based on the write-to-write delay. In one example, the technology increments a write counter corresponding to the memory cell by a first value if the write-to-write delay exceeds a delay threshold and increments the write counter by a second value if the write-to-write delay does not exceed the delay threshold, wherein the second value is greater than the first value, and wherein the write disturb refresh rate is controlled based on the write counter.

公开(公告)号：US20220359030A1

公开(公告)日：2022-11-10

申请号：US17866715

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Yuanyuan Li ,  Rakan Maddah ,  Prashant S. Damle ,  Dany-Sebastien Ly-Gagnon ,  Lunkai Zhang

IPC: G11C29/10 ,  G11C29/12 ,  G11C29/18

Abstract: Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.