公开(公告)号：US20220366962A1

公开(公告)日：2022-11-17

申请号：US17322724

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Rifat FERDOUS ,  Sung-Taeg KANG ,  Rohit S. SHENOY ,  Ali KHAKIFIROOZ ,  Dipanjan BASU

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/409 ,  G11C7/04

Abstract: After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.