公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20220366962A1

公开(公告)日：2022-11-17

申请号：US17322724

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Rifat FERDOUS ,  Sung-Taeg KANG ,  Rohit S. SHENOY ,  Ali KHAKIFIROOZ ,  Dipanjan BASU

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/409 ,  G11C7/04

Abstract: After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.

公开(公告)号：US20240258427A1

公开(公告)日：2024-08-01

申请号：US18605406

申请日：2024-03-14

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20200313001A1

公开(公告)日：2020-10-01

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20230033086A1

公开(公告)日：2023-02-02

申请号：US17791175

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Chen WANG ,  Dipanjan BASU ,  Richard FASTOW ,  Dimitri KIOUSSIS ,  Yi LI ,  Ebony Lynn MAYS ,  Dimitrios PAVLOPOULOS ,  Junyen TEWG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  G11C8/14

Abstract: A memory array including a varying width channel is disclosed. The array includes a plurality of WLs, which are above a layer, where the layer can be, for example, a Select Gate Source (SGS) of the memory array, or an isolation layer to isolate a first deck of the array from a second deck of the array. The channel extends through the plurality of word lines and at least partially through the layer. In an example, the channel comprises a first region and a second region. The first region of the channel has a first width that is at least 1 nm different from a second width of the second region of the channel. In an example, the first region extends through the plurality of word lines, and the second region extends through at least a part of the layer underneath the plurality of word lines. In one case, the first width is at least 1 nm less than a second width of the second region of the channel.

公开(公告)号：US20200279872A1

公开(公告)日：2020-09-03

申请号：US16649593

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Dipanjan BASU ,  Rishabh MEHANDRU ,  Seung Hoon SUNG

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L21/84

Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200227533A1

公开(公告)日：2020-07-16

申请号：US16629555

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Dipanjan BASU

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.

公开(公告)号：US20200083354A1

公开(公告)日：2020-03-12

申请号：US16465763

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Van H. LE ,  Benjamin CHU-KUNG ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.