公开(公告)号：US20250151318A1

公开(公告)日：2025-05-08

申请号：US19018780

申请日：2025-01-13

Applicant: Intel Corporation

Inventor： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC: H10D30/62 ,  H01L21/02 ,  H10D30/69 ,  H10D64/66

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US20240243202A1

公开(公告)日：2024-07-18

申请号：US18622615

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/02

CPC classification number: H01L29/7855 ,  H01L29/4983 ,  H01L29/7848 ,  H01L21/02532 ,  H01L21/02576

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US20210351300A1

公开(公告)日：2021-11-11

申请号：US16868828

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC: H01L29/78 ,  H01L29/49

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.