公开(公告)号：US20240363443A1

公开(公告)日：2024-10-31

申请号：US18768122

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Min Liu ,  Hsueh-Chang Sung ,  Li-Li Su ,  Yee-Chia Yeo

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

公开(公告)号：US20240355898A1

公开(公告)日：2024-10-24

申请号：US18760032

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Lun Min ,  Chang-Miao Liu ,  Xu-Sheng Wu

IPC分类号： H01L29/49 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76834 ,  H01L21/823468 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

公开(公告)号：US20240243202A1

公开(公告)日：2024-07-18

申请号：US18622615

申请日：2024-03-29

申请人： Intel Corporation

发明人： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/02

CPC分类号： H01L29/7855 ,  H01L29/4983 ,  H01L29/7848 ,  H01L21/02532 ,  H01L21/02576

摘要： Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US12034056B2

公开(公告)日：2024-07-09

申请号：US17371907

申请日：2021-07-09

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Chung Chiu ,  Chih-Han Lin ,  Ming-Ching Chiang ,  Chao-Cheng Chen

IPC分类号： H01L29/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.

公开(公告)号：US12015056B2

公开(公告)日：2024-06-18

申请号：US18306359

申请日：2023-04-25

申请人： International Business Machines Corporation

发明人： Yulong Li ,  Paul M. Solomon ,  Siyuranga Koswatta

IPC分类号： H01L29/10 ,  H01L21/28 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/68 ,  H01L29/78 ,  H01L29/788 ,  H01L29/80 ,  H10B12/00 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00

CPC分类号： H01L29/1045 ,  H01L29/0646 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4983 ,  H01L29/516 ,  H01L29/66431 ,  H01L29/66659 ,  H01L29/66977 ,  H01L29/685 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/802 ,  H10B12/30 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/788

摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

公开(公告)号：US12009407B2

公开(公告)日：2024-06-11

申请号：US18303841

申请日：2023-04-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kai Lin ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L21/0259 ,  H01L21/31116 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

摘要： A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

公开(公告)号：US20240153828A1

公开(公告)日：2024-05-09

申请号：US18416069

申请日：2024-01-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu Ling Liao ,  Chung-Chi Ko

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823864 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.

公开(公告)号：US20240145234A1

公开(公告)日：2024-05-02

申请号：US18539977

申请日：2023-12-14

申请人： Novellus Systems, Inc.

发明人： Bhadri N. VARADARAJAN ,  Bo GONG ,  Zhe GUI

IPC分类号： H01L21/02 ,  C23C16/04 ,  C23C16/32 ,  C23C16/452 ,  C23C16/505 ,  C23C16/511 ,  H01L21/768 ,  H01L29/49

CPC分类号： H01L21/02167 ,  C23C16/045 ,  C23C16/325 ,  C23C16/452 ,  C23C16/505 ,  C23C16/511 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/76831 ,  H01L21/76834 ,  H01L29/4983 ,  H01L29/4991 ,  H01L21/7682 ,  H01L2221/1047

摘要： Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.

公开(公告)号：USRE49954E1

公开(公告)日：2024-04-30

申请号：US17338459

申请日：2021-06-03

申请人： TESSERA LLC

发明人： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L27/088 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78696

摘要： A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.

公开(公告)号：US11881519B2

公开(公告)日：2024-01-23

申请号：US17826380

申请日：2022-05-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Nam Gyu Cho ,  Rak Hwan Kim ,  Hyeok-Jun Son ,  Do Sun Lee ,  Won Keun Chung

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/786

CPC分类号： H01L29/4983 ,  H01L21/28132 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

摘要： A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.