公开(公告)号：US20250159932A1

公开(公告)日：2025-05-15

申请号：US18389427

申请日：2023-11-14

Applicant: Intel Corporation

Inventor： Chiao-Ti HUANG ,  Swapnadip GHOSH ,  Matthew PRINCE ,  Omair SAADAT ,  Yulia GOTLIB ,  Rajaram PAI ,  Reza BAYATI ,  Ryan PEARCE ,  Lin HU

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having metal gate cut plug structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure includes silicon and oxygen, with oxygen in direct contact with a metal-containing layer of the gate electrode.

公开(公告)号：US20250151318A1

公开(公告)日：2025-05-08

申请号：US19018780

申请日：2025-01-13

Applicant: Intel Corporation

Inventor： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC: H10D30/62 ,  H01L21/02 ,  H10D30/69 ,  H10D64/66

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US20240243202A1

公开(公告)日：2024-07-18

申请号：US18622615

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/02

CPC classification number: H01L29/7855 ,  H01L29/4983 ,  H01L29/7848 ,  H01L21/02532 ,  H01L21/02576

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

公开(公告)号：US20210351300A1

公开(公告)日：2021-11-11

申请号：US16868828

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： Ritesh K. DAS ,  Kiran CHIKKADI ,  Ryan PEARCE

IPC: H01L29/78 ,  H01L29/49

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.