公开(公告)号：US20250077352A1

公开(公告)日：2025-03-06

申请号：US18952668

申请日：2024-11-19

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS ,  Lawrence D. BLANKENBECKLER ,  Ronald ANDERSON ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/4096

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

公开(公告)号：US20210382638A1

公开(公告)日：2021-12-09

申请号：US17411944

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Ronald ANDERSON ,  Lawrence D. BLANKENBECKLER ,  Pietro FRIGO ,  Jaemon FRANKO ,  Sreenivas MANDAVA

IPC: G06F3/06

Abstract: A memory system includes a memory device having a memory array that stores data based on address bits, including a row address. The memory system includes a memory controller having scrambler circuitry to apply a data mask to scramble data to be stored in the memory array. The scrambler can apply the data mask to scramble data for a write operation. The data scrambler can unscramble data for a read operation. The data mask has a pseudorandom pattern based at least in part on the row address of the data to be written or read.

公开(公告)号：US20210365316A1

公开(公告)日：2021-11-25

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS ,  Lawrence BLANKENBECKLER ,  Ronald ANDERSON ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/406

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.