公开(公告)号：US20250077352A1

公开(公告)日：2025-03-06

申请号：US18952668

申请日：2024-11-19

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS ,  Lawrence D. BLANKENBECKLER ,  Ronald ANDERSON ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/4096

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

公开(公告)号：US20210141692A1

公开(公告)日：2021-05-13

申请号：US17156399

申请日：2021-01-22

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Wei P. CHEN ,  Bill NALE ,  James A. McCALL

IPC: G06F11/10

Abstract: A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N−M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.

公开(公告)号：US20190213148A1

公开(公告)日：2019-07-11

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX ,  Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Chong J. ZHAO ,  Suneeta SAH ,  Pete D. VOGT ,  John R. GOLES

IPC: G06F13/16 ,  G06F13/40 ,  G11C14/00 ,  G11C11/4096

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096 ,  G11C14/0009 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20190018809A1

公开(公告)日：2019-01-17

申请号：US16046587

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Bill NALE ,  Raj K. RAMANUJAN ,  Muthukumar P. SWAMINATHAN ,  Tessil THOMAS ,  Taarinya POLEPEDDI

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F9/46 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/0802 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

公开(公告)号：US20160148653A1

公开(公告)日：2016-05-26

申请号：US15011383

申请日：2016-01-29

Applicant: INTEL CORPORATION

Inventor： Bill NALE

IPC: G11C5/14

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for using a pre-clock enable (pre-CKE) command for power management modes. A host memory controller sends a pre-CKE command to a memory module over a bus indicating at least one power management operation to perform. The host memory controller further asserts a clock enable (CKE) signal to the memory module over the bus after sending the pre-CKE command to cause a memory module controller to execute the indicated at least one power management operation in response to the CKE signal.

Abstract translation: 提供了一种用于对电源管理模式使用前置时钟使能（pre-CKE）命令的方法和装置。 主机存储器控制器通过总线向存储器模块发送预CKE命令，指示执行至少一个电源管理操作。 主机存储器控制器在发送预先CKE命令之后进一步通过总线断言对存储器模块的时钟使能（CKE）信号，以使存储器模块控制器响应于CKE信号执行所指示的至少一个电源管理操作。

公开(公告)号：US20220189532A1

公开(公告)日：2022-06-16

申请号：US17686287

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20210336767A1

公开(公告)日：2021-10-28

申请号：US17359152

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Raghunandan MAKARAM ,  Kirk S. YAP ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE ,  Jacob DOWECK

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  G11C29/42 ,  G11C29/12

Abstract: A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.

公开(公告)号：US20210286561A1

公开(公告)日：2021-09-16

申请号：US17336996

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Bill NALE

IPC: G06F3/06

Abstract: For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.

公开(公告)号：US20210005245A1

公开(公告)日：2021-01-07

申请号：US16879583

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/406 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US20190042499A1

公开(公告)日：2019-02-07

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.