公开(公告)号：US20240159829A1

公开(公告)日：2024-05-16

申请号：US18551879

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Min LIU ,  Jaemon FRANKO ,  Xia JIN ,  Xiang LI ,  Jiaqi LIU ,  Krishna SURYA

IPC: G01R31/3185

CPC classification number: G01R31/318591 ,  G01R31/31853 ,  G01R31/318547

Abstract: A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.

公开(公告)号：US20240241854A1

公开(公告)日：2024-07-18

申请号：US18619217

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Garrett CLAY ,  Jaemon FRANKO ,  Heung-for CHENG

IPC: G06F15/80 ,  G06F1/20

CPC classification number: G06F15/80 ,  G06F1/206

Abstract: Some aspects of the present disclosure relate to an apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores and to determine a first processor core of the plurality of processor cores to execute a first work-load based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

公开(公告)号：US20210382638A1

公开(公告)日：2021-12-09

申请号：US17411944

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Ronald ANDERSON ,  Lawrence D. BLANKENBECKLER ,  Pietro FRIGO ,  Jaemon FRANKO ,  Sreenivas MANDAVA

IPC: G06F3/06

Abstract: A memory system includes a memory device having a memory array that stores data based on address bits, including a row address. The memory system includes a memory controller having scrambler circuitry to apply a data mask to scramble data to be stored in the memory array. The scrambler can apply the data mask to scramble data for a write operation. The data scrambler can unscramble data for a read operation. The data mask has a pseudorandom pattern based at least in part on the row address of the data to be written or read.