公开(公告)号：US20190179779A1

公开(公告)日：2019-06-13

申请号：US16275625

申请日：2019-02-14

Applicant: Intel Corporation

Inventor： Andrew FRIEDLEY ,  Sayantan SUR ,  Ravindra Babu GANAPATHI ,  Travis HAMILTON ,  Keith D. UNDERWOOD

IPC: G06F13/16 ,  G06F12/0802 ,  G06F9/48

Abstract: Examples include a method of managing storage for triggered operations. The method includes receiving a request to allocate a triggered operation; if there is a free triggered operation, allocating the free triggered operation; if there is no free triggered operation, recovering one or more fired triggered operations, freeing one or more of the recovered triggered operations, and allocating one of the freed triggered operations; configuring the allocated triggered operation; and storing the configured triggered operation in a cache on an input/output (I/O) device for subsequent asynchronous execution of the configured triggered operation.

公开(公告)号：US20190213146A1

公开(公告)日：2019-07-11

申请号：US16353759

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Nusrat ISLAM ,  Gengbin ZHENG ,  Sayantan SUR ,  Maria GARZARAN ,  Akhil LANGER

IPC: G06F13/16 ,  G06F16/901

CPC classification number: G06F13/16 ,  G06F16/9024 ,  G06F2213/16

Abstract: Examples include a computing system having an input/output (I/O) device including a plurality of counters, each counter operating as one of a completion counter and a trigger counter, a processing device; and a memory device. The memory device stores instructions that, in response to execution by the processing device, cause the processing device to represent a plurality of triggered operations of collective communication for high-performance computing executable by the I/O device as a directed acyclic graph stored in the memory device, with triggered operations represented as vertices of the directed acyclic graph and dependencies between triggered operations represented as edges of the directed acyclic graph; traverse the directed acyclic graph using a first process to identify and mark vertices that can share a completion counter; and traverse the directed acyclic graph using a second process to assign a completion counter and a trigger counter for each vertex.

公开(公告)号：US20220351326A1

公开(公告)日：2022-11-03

申请号：US17853711

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Todd RIMMER ,  Mark DEBBAGE ,  Bruce G. WARREN ,  Sayantan SUR ,  Nayan Amrutlal SUTHAR ,  Ajaya Durg

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.