公开(公告)号：US20170054633A1

公开(公告)日：2017-02-23

申请号：US15256390

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Keith D. UNDERWOOD ,  Steffen KOSINSKI ,  Jaroslaw TOPP ,  Jan UERPMANN ,  Michael REDEKER

IPC: H04L12/721 ,  H04L12/801

CPC classification number: H04L45/38 ,  G06F13/385 ,  G06F15/167 ,  H04L1/12 ,  H04L1/1835 ,  H04L43/103 ,  H04L45/60 ,  H04L47/34 ,  H04L67/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.

Abstract translation: 提出了与高性能计算系统中节点之间的通信和内部节点之间相关的方法。 节点间处理单元与网络控制器接口之间的消息交换处理时间缩短。 在网络接口控制器中管理应用程序状态所需的资源被最小化。 在网络接口控制器中，多个上下文被复用到一个物理的直接存储器访问引擎中。 通过使用多个独立的高速缓存来加速网络接口控制器中的虚拟到物理地址转换，每个级别的页表层次结构缓存在独立的高速缓存中。 提供了一种用于在处理单元和网络控制器接口之间分布的数据结构的存储器管理方案。 通过将发送序列号空间限制到当前的飞行中消息来减少实现端到端可靠性所需的状态。

公开(公告)号：US20190179779A1

公开(公告)日：2019-06-13

申请号：US16275625

申请日：2019-02-14

Applicant: Intel Corporation

Inventor： Andrew FRIEDLEY ,  Sayantan SUR ,  Ravindra Babu GANAPATHI ,  Travis HAMILTON ,  Keith D. UNDERWOOD

IPC: G06F13/16 ,  G06F12/0802 ,  G06F9/48

Abstract: Examples include a method of managing storage for triggered operations. The method includes receiving a request to allocate a triggered operation; if there is a free triggered operation, allocating the free triggered operation; if there is no free triggered operation, recovering one or more fired triggered operations, freeing one or more of the recovered triggered operations, and allocating one of the freed triggered operations; configuring the allocated triggered operation; and storing the configured triggered operation in a cache on an input/output (I/O) device for subsequent asynchronous execution of the configured triggered operation.