公开(公告)号：US20180101323A1

公开(公告)日：2018-04-12

申请号：US15656885

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Donia Sebastian ,  Simon D. Ramage ,  Curtis A. Gittens ,  Scott Nelson ,  David B. Carlton ,  Kai-Uwe Schmidt

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0688

Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

公开(公告)号：US20190042112A1

公开(公告)日：2019-02-07

申请号：US15927042

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Sarvesh Varakabe Gangadhar ,  Feng Zhu ,  Xin Guo ,  Simon D. Ramage ,  Ning Wu ,  Robert E. Frickey, III

IPC: G06F3/06 ,  G11C16/34 ,  G06F11/30

Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.

公开(公告)号：US09727267B1

公开(公告)日：2017-08-08

申请号：US15277524

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Donia Sebastian ,  Simon D. Ramage ,  Curtis A. Gittens ,  Scott Nelson ,  David B. Carlton ,  Kai-Uwe Schmidt

IPC: G11C5/14 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0688

Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

公开(公告)号：US10095432B2

公开(公告)日：2018-10-09

申请号：US15656885

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Donia Sebastian ,  Simon D. Ramage ,  Curtis A. Gittens ,  Scott Nelson ,  David B. Carlton ,  Kai-Uwe Schmidt

IPC: G11C5/14 ,  G06F3/06

Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.