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    ENERGY EFFICIENT STORAGE OF ERROR-CORRECTION-DETECTION INFORMATION
    1.
    发明公开
    ENERGY EFFICIENT STORAGE OF ERROR-CORRECTION-DETECTION INFORMATION 审中-公开

    公开(公告)号：US20240354191A1

    公开(公告)日：2024-10-24

    申请号：US18649031

    申请日：2024-04-29

    Applicant: Rambus Inc.

    Inventor： Michael Raymond MILLER ,  Stephen Magee ,  John Eric Linstadt

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

    Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES
    2.
    发明公开
    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES 审中-公开

    公开(公告)号：US20240354012A1

    公开(公告)日：2024-10-24

    申请号：US18760849

    申请日：2024-07-01

    Applicant: Ambiq Micro, Inc.

    Inventor： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

    Storage system
    3.
    发明授权
    Storage system 有权

    公开(公告)号：US12124712B2

    公开(公告)日：2024-10-22

    申请号：US18179563

    申请日：2023-03-07

    Applicant: Hitachi, Ltd.

    Inventor： Naoya Okada ,  Kentaro Shimada ,  Yuki Kotake ,  Yukiyoshi Takamura

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

    Abstract: A storage system includes a storage controller and a plurality of storage drives. The storage controller holds power management information for managing power supplied to the storage system and power consumption of an operating mounted device of the storage system, and definition information for defining a relationship between power states and power consumption of the plurality of storage drives. The storage controller determines a power budget that can be supplied to the plurality of storage drives, based on the power management information according to a change in a configuration of the storage system, and determines a power state of each of the plurality of storage drives based on the power budget and the definition information.

    TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS
    4.
    发明公开
    TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240345744A1

    公开(公告)日：2024-10-17

    申请号：US18638480

    申请日：2024-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0673

    Abstract: Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

    Asymmetric time division peak power management (TD-PPM) timing windows
    6.
    发明授权
    Asymmetric time division peak power management (TD-PPM) timing windows 有权

    公开(公告)号：US12118219B2

    公开(公告)日：2024-10-15

    申请号：US17903189

    申请日：2022-09-06

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay Benisty ,  Yossi Yoseph Hassan

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0631 ,  G06F3/0673

    Abstract: A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.

    Reducing energy consumption of self-managed DRAM modules
    7.
    发明授权
    Reducing energy consumption of self-managed DRAM modules 有权

    公开(公告)号：US12112049B2

    公开(公告)日：2024-10-08

    申请号：US18051150

    申请日：2022-10-31

    Applicant: ScaleFlux, Inc.

    Inventor： Kelly Fitzpatrick ,  Yang Liu ,  Tong Zhang

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679

    Abstract: A self-managed DRAM module configured to reduce energy consumption. A module is described that includes a plurality of DDR channels and a management engine configured to read and write data blocks to DDR channels according to a process that includes: allocating a set of sub-channels for each DDR channel, wherein each sub-channel includes a subset of the set of DRAM chips; wherein a write operation of a data block includes: encoding the data block to generate an ECC codeword; and writing the ECC codeword into the subset of DRAM chips of a specified sub-channel; and wherein a read operation of the data block includes: reading the ECC codeword from the subset of DRAM chips of the specified sub-channel; and decoding the ECC codeword to obtain the data block.

    Adaptive tuning of memory device clock rates based on dynamic parameters
    8.
    发明授权
    Adaptive tuning of memory device clock rates based on dynamic parameters 有权

    公开(公告)号：US12112048B2

    公开(公告)日：2024-10-08

    申请号：US17939186

    申请日：2022-09-07

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay Benisty ,  Ariel Navon ,  Alexander Bazarsky ,  David Avraham

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

    Data storage system with intelligent power management
    10.
    发明授权
    Data storage system with intelligent power management 有权

    公开(公告)号：US12099730B2

    公开(公告)日：2024-09-24

    申请号：US18321893

    申请日：2023-05-23

    Applicant: PROMISE TECHNOLOGY, INC.

    Inventor： Zhi-Yu Wu ,  Cheng-Chou Wang ,  Che-Jen Wang

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A data storage system with intelligent power management includes a plurality of data storage devices and a controller. Each data storage device is capable of operating in one of (N+1) power saving functions where N is an integer larger than 1. The (N+1) power saving functions sequentially correspond to from the 0th to the Nth power saving levels. The controller reads a user-setting power saving level (I) where I is an integer index ranging from 0 to N. The controller reads a current power saving level (J) of a current power saving function of one of the plurality of data storage devices where J is an integer index ranging from 0 to N. The controller controls said one data storage device to operate in one power saving function among the (N+1) power saving functions according to the user-setting power saving level (I) and the current power saving level (J).

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