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公开(公告)号:US20190042112A1
公开(公告)日:2019-02-07
申请号:US15927042
申请日:2018-03-20
Applicant: Intel Corporation
Inventor: Sarvesh Varakabe Gangadhar , Feng Zhu , Xin Guo , Simon D. Ramage , Ning Wu , Robert E. Frickey, III
Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.
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公开(公告)号:US09183091B2
公开(公告)日:2015-11-10
申请号:US13628356
申请日:2012-09-27
Applicant: Intel Corporation
Inventor: Ning Wu , Robert E. Frickey , Hanmant P. Belgal , Xin Guo
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0647 , G06F3/065 , G06F3/0688 , G06F11/1417
Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.
Abstract translation: 根据一种配置,存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑,检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知,以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知,检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。
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公开(公告)号:US10236069B2
公开(公告)日:2019-03-19
申请号:US15627928
申请日:2017-06-20
Applicant: Intel Corporation
Inventor: Ning Wu , Robert E. Frickey
Abstract: An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.
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公开(公告)号:US10067829B2
公开(公告)日:2018-09-04
申请号:US14106571
申请日:2013-12-13
Applicant: INTEL CORPORATION
Inventor: Robert E. Frickey, III , Wei Fang , Ning Wu
Abstract: Embodiments include apparatuses, method, and systems for organizing individual memory dice of a memory device into a plurality of virtual dice and designating one of the virtual dice of the memory device for storage of redundancy information. In one embodiment, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a plurality of data virtual dice for storing data. The memory controller may further include input/output logic to write data to the data virtual dice of the non-volatile memory device, and redundancy information logic to generate redundancy information based on the data and to write the redundancy information to the redundancy virtual die of the non-volatile memory device.
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公开(公告)号:US20170123946A1
公开(公告)日:2017-05-04
申请号:US14932870
申请日:2015-11-04
Applicant: Intel Corporation
Inventor: Ning Wu , Xin Guo , Ramkarthik Ganesan , Pranav Kalavade , Robert Frickey
IPC: G06F11/20
CPC classification number: G06F11/2094 , G06F11/141 , G06F11/1441 , G06F12/0238 , G06F12/0804 , G06F12/0868 , G06F2201/805 , G06F2212/1016 , G06F2212/1032 , G06F2212/1044 , G06F2212/1048 , G06F2212/214 , G06F2212/222 , G06F2212/7203 , G06F2212/7204 , G06F2212/7211 , G11C2211/5641
Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.
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公开(公告)号:US11099760B2
公开(公告)日:2021-08-24
申请号:US15842799
申请日:2017-12-14
Applicant: Intel Corporation
Inventor: Shankar Natarajan , Ning Wu
IPC: G06F3/06 , G11C16/34 , G06F16/11 , G06F16/174 , G11C16/26 , G11C29/52 , G11C16/04 , G11C16/10 , G06F11/10
Abstract: Techniques for performing background refresh for storage devices using a timestamp from the host are described. In one example, a method involves receiving a timestamp from a host, storing the timestamp in a storage device, and determining a retention time for data stored in one or more blocks of the storage device based on the timestamp relative to a second timestamp indicating when the data was written to the one or more blocks. In response to determining the retention time exceeds a threshold, the storage device moves the data to one or more other blocks of the storage device, which can include interleaving the refresh writes with activity from the host.
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公开(公告)号:US10303571B2
公开(公告)日:2019-05-28
申请号:US14932870
申请日:2015-11-04
Applicant: Intel Corporation
Inventor: Ning Wu , Xin Guo , Ramkarthik Ganesan , Pranav Kalavade , Robert Frickey
IPC: G06F11/00 , G06F11/20 , G06F12/02 , G06F11/14 , G06F12/0804 , G06F12/0868
Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.
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公开(公告)号:US10185511B2
公开(公告)日:2019-01-22
申请号:US14979125
申请日:2015-12-22
Applicant: Intel Corporation
Inventor: Neeraj Sharma , Ning Wu , Steven E. Wells
Abstract: Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the operational characteristic satisfies a low threshold and a high threshold. If the operational characteristic does satisfy the low threshold, the solid state drive throttles high power memory accesses requests while not throttle low power memory access requests. If the operational characteristic satisfies a high threshold, the solid state drive is configured to throttle all memory accesses. The operational characteristic may be embodied as, for example, a temperature of the solid state drive.
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公开(公告)号:US09817600B2
公开(公告)日:2017-11-14
申请号:US15377200
申请日:2016-12-13
Applicant: Intel Corporation
Inventor: Ning Wu , Robert E. Frickey , Hanmant P. Belgal , Xin Guo
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0647 , G06F3/065 , G06F3/0688 , G06F11/1417
Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.
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公开(公告)号:US20170177262A1
公开(公告)日:2017-06-22
申请号:US14979125
申请日:2015-12-22
Applicant: Intel Corporation
Inventor: Neeraj Sharma , Ning Wu , Steven E. Wells
IPC: G06F3/06
CPC classification number: G06F3/0634 , G06F3/0616 , G06F3/0653 , G06F3/0673 , G06F3/0679 , G11C7/04
Abstract: Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the operational characteristic satisfies a low threshold and a high threshold. If the operational characteristic does satisfy the low threshold, the solid state drive throttles high power memory accesses requests while not throttle low power memory access requests. If the operational characteristic satisfies a high threshold, the solid state drive is configured to throttle all memory accesses. The operational characteristic may be embodied as, for example, a temperature of the solid state drive.
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