公开(公告)号：US20250008740A1

公开(公告)日：2025-01-02

申请号：US18216490

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Wriddhi Chakraborty ,  Sourav Dutta ,  Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  Gilbert Dewey ,  Uygar Avci

IPC: H10B53/20 ,  H10B53/30

Abstract: An integrated circuit device includes a stack of capacitors with a vertical first electrode coupled to a stack of individual second electrodes by an insulating storage material between first and second electrodes, and an access transistor coaxially aligned with, and coupled to, the vertical first electrode. The storage material may be a ferroelectric material. A gate dielectric of the access transistor may be around, and coaxial with, a channel region. The channel region may be vertically oriented and coaxial with the first electrode. A second access transistor may be similarly aligned with the first electrode and the stack of capacitors with the capacitor stack between the transistors. A channel of the second transistor may be around, and coaxial with, a gate dielectric. The transistors and capacitor stack may be in arrays of transistors and capacitor stacks. A self-aligned process may be used to form the capacitor and transistor arrays.

公开(公告)号：US20240114694A1

公开(公告)日：2024-04-04

申请号：US17937043

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sourav Dutta ,  Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Christopher M. Neumann ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Brian S. Doyle

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.

公开(公告)号：US20240113101A1

公开(公告)日：2024-04-04

申请号：US17936990

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sourav Dutta ,  Nazila Haratipour ,  Vachan Kumar ,  Uygar E. Avci ,  Shriram Shivaraman ,  Sou-Chi Chang

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/55 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/0673

Abstract: Techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. A given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. A gate structure extends in a second direction over the one or more semiconductor regions. A capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. The capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.