公开(公告)号：US20170286122A1

公开(公告)日：2017-10-05

申请号：US15089232

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Lisa K. Wu ,  Tae Jun Ham ,  Nadathur Rajagopalan Satish ,  Narayanan Sundaram

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/3877 ,  G06F2209/509 ,  G06T1/20 ,  Y02D10/22

Abstract: A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor.