公开(公告)号：US20190107873A1

公开(公告)日：2019-04-11

申请号：US16191691

申请日：2018-11-15

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Darius D. Gaskins

IPC: G06F1/26 ,  G06F1/24 ,  G06F13/36 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F15/82 ,  G06F15/163 ,  G06F9/50 ,  G06F9/445

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

公开(公告)号：US20180357110A1

公开(公告)日：2018-12-13

申请号：US16107691

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： GUY M. THERIEN ,  MICHAEL D. POWELL ,  VENKATESH RAMANI ,  ARIJIT BISWAS ,  GUY G. SOTOMAYOR

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044 ,  Y02D10/22

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US10067547B2

公开(公告)日：2018-09-04

申请号：US14757865

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Enrique G. Castro-Leon

IPC: G06F1/26 ,  G06F1/32 ,  H04L29/08 ,  G06F9/50

CPC classification number: G06F1/266 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/5094 ,  H04L67/1097 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: Servers, storage medium and methods associated with control of power management services of remote servers of a remote computing service are disclosed herein. In embodiments, an apparatus to control power consumption of computer hardware may comprise a datacenter management control module to receive a request to increase capacity of a server pool from a computing device; determine an available server with available capacity that includes a power management controller to collect power consumption data for one or more of a power supply, a memory, or a processor of the available server, wherein the available server may be a remote cloud server in a different subnet than the server pool and the computing device; add or facilitate addition of the available server to the server pool; and transmit power management commands to the server added to the server pool to at least partially control power consumption of the server provided with the power management commands. Other embodiments may be disclosed or claimed.

公开(公告)号：US10061709B2

公开(公告)日：2018-08-28

申请号：US14936209

申请日：2015-11-09

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1027 ,  G06F9/50 ,  G06F13/16

CPC classification number: G06F12/1009 ,  G06F9/5016 ,  G06F12/1027 ,  G06F13/1684 ,  G06F2212/65 ,  G06F2212/657 ,  Y02D10/14 ,  Y02D10/22

Abstract: Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

公开(公告)号：US10054999B2

公开(公告)日：2018-08-21

申请号：US15470454

申请日：2017-03-27

Applicant: Facebook, Inc.

Inventor： Eran Tal ,  Benoit M. Schillings ,  Michael John McKenzie Toksvig

IPC: G06F1/32 ,  G06F9/50 ,  H04W52/02

CPC classification number: G06F1/324 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3209 ,  G06F1/325 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  H04W52/0258 ,  H05K999/99 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/166 ,  Y02D70/22 ,  Y02D70/26

Abstract: In one embodiment, a method includes a server receiving activity data from a plurality of computing devices, wherein the activity data is associated with running a particular application; identifying, based on the activity data, a pattern of execution related to executing one or more sequences of instructions associated with running the particular application; determining, based on the pattern of execution, a clocking policy for running the particular application, wherein the clocking policy is configured to modify a clock speed of one or more processors of a particular computing device while running the particular application; and sending the clocking policy to the particular computing device.

公开(公告)号：US10054997B2

公开(公告)日：2018-08-21

申请号：US14869689

申请日：2015-09-29

Applicant: Honeywell International Inc.

Inventor： Gregory E. Stewart ,  Sohail Nazari ,  Robert Paul Cartier Dooner

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5083 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

Abstract: A method includes identifying demand for computing resources provided by multiple computing devices and identifying operating states or modes for the computing devices based on the demand using a multivariable controller. The multivariable controller is configured to determine how to alter multiple manipulated variables in order to create changes to multiple controlled variables. The multiple manipulated variables include the operating states or modes of the computing devices, and the multiple controlled variables include a power consumption of the computing devices and a response time of the computing devices. Each of the computing devices could include one or more processing units, and each of the computing devices or processing units could be configured to selectively operate in one of the operating states or modes. The method could also include generating a profile identifying a number of computing devices or processing units to operate in each of the operating states or modes.

公开(公告)号：US20180203734A1

公开(公告)日：2018-07-19

申请号：US15743635

申请日：2016-07-05

Applicant: RAMBUS, INC.

Inventor： Keith LOWERY

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02

CPC classification number: G06F9/5016 ,  G06F8/453 ,  G06F9/3004 ,  G06F9/3889 ,  G06F9/50 ,  G06F12/023 ,  G06F2209/502 ,  G06F2212/2542 ,  Y02D10/22

Abstract: A method and system for thread aware, class aware, and topology aware memory allocations. Embodiments include a compiler configured to generate compiled code (e.g., for a runtime) that when executed allocates memory on a per class per thread basis that is system topology (e.g., for non-uniform memory architecture (NUMA)) aware. Embodiments can further include an executable configured to allocate a respective memory pool during runtime for each instance of a class for each thread. The memory pools are local to a respective processor, core, etc., where each thread executes.

公开(公告)号：US10019216B2

公开(公告)日：2018-07-10

申请号：US13583160

申请日：2011-03-29

Applicant: Masaya Fujiwaka

Inventor： Masaya Fujiwaka

IPC: G06F3/14 ,  G06F9/50

CPC classification number: G06F3/1423 ,  G06F9/5094 ,  G09G2330/021 ,  G09G2360/04 ,  Y02D10/22

Abstract: An information processing terminal includes a plurality of displays, each displaying an application screen, and control means. The control means determines a display on which a new application is to be started from the plurality of displays on the basis of the amount of the resources consumed by the information processing terminal.

公开(公告)号：US20180157503A1

公开(公告)日：2018-06-07

申请号：US15866234

申请日：2018-01-09

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Kenneth Chong Yin Tan

IPC: G06F9/445 ,  G06F9/50

CPC classification number: G06F9/44505 ,  G06F9/445 ,  G06F9/5044 ,  Y02D10/22

Abstract: A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.

公开(公告)号：US09990200B2

公开(公告)日：2018-06-05

申请号：US15082359

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/3009 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/34 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/5038 ,  G06F9/5077 ,  G06F2209/506 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.