公开(公告)号：US20170286122A1

公开(公告)日：2017-10-05

申请号：US15089232

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Lisa K. Wu ,  Tae Jun Ham ,  Nadathur Rajagopalan Satish ,  Narayanan Sundaram

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/3877 ,  G06F2209/509 ,  G06T1/20 ,  Y02D10/22

Abstract: A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor.

公开(公告)号：US10198264B2

公开(公告)日：2019-02-05

申请号：US14969864

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Deborah T. Marr ,  Jong Soo Park ,  Nadathur Rajagopalan Satish ,  Mikhail Smelyanskiy ,  Michael Anderson ,  Mostofa Ali Patwary ,  Narayanan Sundaram ,  Sheng Li

IPC: G06F9/30

Abstract: A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.

公开(公告)号：US20170185403A1

公开(公告)日：2017-06-29

申请号：US14757776

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Michael J. Anderson ,  Sheng R. Li ,  Jong Soo Park ,  Md Mostofa Ali Patwary ,  Nadathur Rajagopalan Satish ,  Mikhail Smelyanskiy ,  Narayanan Sundaram

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/3005 ,  G06F9/3877 ,  G06F12/0875 ,  G06F16/9014 ,  G06F17/10 ,  G06F2212/452

Abstract: A processor includes a front end to receive an instruction, a decoder to decode the instruction, a set operations logic unit (SOLU) to execute the instruction, and a retirement unit to retire the instruction. The SOLU includes logic to store a first set of key-value pairs in a content-associative data structure, to receive a second set of key-value pairs, and to identify key-value pairs in the two sets with matching keys. The SOLU includes logic to add the second set of key-value pairs to the first set to produce an output set, and to apply an operation to the values of key-value pairs with matching keys, generating a single value for the matching key. The SOLU includes logic to produce an output set that includes key-value pairs from the first set with matching keys, and to discard key-value pairs from the first set with unique keys.

公开(公告)号：US20170168827A1

公开(公告)日：2017-06-15

申请号：US14969864

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Deborah T. Marr ,  Jong Soo Park ,  Nadathur Rajagopalan Satish ,  Mikhail Smelyanskiy ,  Michael Anderson ,  Mostofa Ali Patwary ,  Narayanan Sundaram ,  Sheng Li

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145

Abstract: A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.