公开(公告)号：US20250006652A1

公开(公告)日：2025-01-02

申请号：US18346098

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Francisco Maya ,  Bhaskar Jyoti Krishnatreya ,  Tan Nguyen ,  Siyan Dong ,  Alveera Gill ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

公开(公告)号：US20250006653A1

公开(公告)日：2025-01-02

申请号：US18346108

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Bhaskar Jyoti Krishnatreya ,  Francisco Maya ,  Siyan Dong ,  Alveera Gill ,  Tan Nguyen ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.