公开(公告)号：US20250006652A1

公开(公告)日：2025-01-02

申请号：US18346098

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Francisco Maya ,  Bhaskar Jyoti Krishnatreya ,  Tan Nguyen ,  Siyan Dong ,  Alveera Gill ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

公开(公告)号：US20250006651A1

公开(公告)日：2025-01-02

申请号：US18345820

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Francisco Maya ,  Khant Minn ,  Suresh V. Pothukuchi ,  Arnab Sarkar ,  Mohit Bhatia ,  Bhaskar Jyoti Krishnatreya ,  Siyan Dong

IPC: H01L23/544 ,  H01L23/00

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a fiducial having a length size greater than a width size of the fiducial, wherein the fiducial comprises at least one first area and at least one second area, wherein the at least one first area is to stop light from a light source and the at least one second area is to pass light from the light source during a determination of an alignment between the first integrated circuit device and a second integrated circuit device.

公开(公告)号：US20250006653A1

公开(公告)日：2025-01-02

申请号：US18346108

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Bhaskar Jyoti Krishnatreya ,  Francisco Maya ,  Siyan Dong ,  Alveera Gill ,  Tan Nguyen ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.

公开(公告)号：US20240006332A1

公开(公告)日：2024-01-04

申请号：US17856801

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Dimitrios Antartis ,  Nitin A. Deshpande ,  Siyan Dong ,  Omkar Karhade ,  Gwang-soo Kim ,  Shawna Liff ,  Siddhartha Mal ,  Debendra Mallik ,  Khant Minn ,  Haris Khan Niazi ,  Arnab Sarkar ,  Yi Shi ,  Botao Zhang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L24/08 ,  H01L23/481 ,  H01L2224/08145 ,  H01L2223/54426

Abstract: An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component. The IC die comprises a substrate material layer and a die metallization level between the substrate material layer and host component. The IC die includes an upper die alignment fiducial between the die metallization level and host component. The upper die alignment fiducial at least partially overlaps one or more metallization features within the die metallization level. In embodiments, at least two orthogonal edges of the upper die alignment fiducial do not overlap any of the metallization features within the die metallization level. In embodiments, the IC die includes a lower die alignment fiducial between the substrate material layer and the die metallization level. The lower die alignment fiducial may at least partially overlap one or more second metallization features within a second die metallization level of the IC die.