公开(公告)号：US20250006652A1

公开(公告)日：2025-01-02

申请号：US18346098

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Francisco Maya ,  Bhaskar Jyoti Krishnatreya ,  Tan Nguyen ,  Siyan Dong ,  Alveera Gill ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

公开(公告)号：US12119317B2

公开(公告)日：2024-10-15

申请号：US17032469

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Nagatoshi Tsunoda ,  Shawna M. Liff ,  Sairam Agraharam

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/0823 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

公开(公告)号：US20240063147A1

公开(公告)日：2024-02-22

申请号：US17891704

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Omkar Karhade ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Xavier Brun ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/564 ,  H01L24/08 ,  H01L24/24 ,  H01L25/0652 ,  H01L24/19 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/291 ,  H01L2224/08145 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/37001 ,  H01L2224/24145 ,  H01L24/73 ,  H01L2224/73259 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2224/2499

Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

公开(公告)号：US20240063076A1

公开(公告)日：2024-02-22

申请号：US17891727

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Kimin Jun ,  Adel Elsherbini ,  Tushar Talukdar ,  Feras Eid ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Xavier Brun

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L24/08 ,  H01L23/3736 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/481 ,  H01L24/32 ,  H01L24/29 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2224/29147 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29193 ,  H01L2224/29186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.

公开(公告)号：US20240429199A1

公开(公告)日：2024-12-26

申请号：US18340635

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Yi Shi ,  Bhaskar Jyoti Krishnatreya ,  Feras Eid ,  Xavier Brun ,  Johanna Swan

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68 ,  H01L21/683

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to self-align batch pick and place die bonding. Disclosed is an apparatus comprising a fluid dispensing assembly to dispense first amounts of water onto first hydrophilic regions of a first semiconductor wafer at a first point in time, the first hydrophilic regions having a first arrangement, and dispense second amounts of water onto second hydrophilic regions of a second semiconductor wafer at a second point in time, the second hydrophilic regions having a second arrangement, and a pick-and-place assembly to simultaneously position, at the first point in time, a first batch of dies corresponding to the first arrangement onto the first amounts of water dispensed on the first semiconductor wafer, and simultaneously position, at the second point in time, a second batch of dies corresponding to the second arrangement onto the second amounts of water dispensed on the second semiconductor wafer.

公开(公告)号：US20240063179A1

公开(公告)日：2024-02-22

申请号：US17821009

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Vasanth Valavala ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Debendra Mallik ,  Feras Eid ,  Xavier Francois Brun ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/20 ,  H01L24/08 ,  H01L21/568 ,  H01L24/19 ,  H01L24/06 ,  H01L2224/221 ,  H01L2224/211 ,  H01L2224/08225 ,  H01L2224/19 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.

公开(公告)号：US20240061194A1

公开(公告)日：2024-02-22

申请号：US17821019

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  David Hui ,  Haris Khan Niazi ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Henning Braunisch ,  Shawna M. Liff ,  Jiraporn Seangatith ,  Johanna M. Swan ,  Krishna Vasanth Valavala ,  Xavier Francois Brun ,  Feras Eid

IPC: G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4204

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

公开(公告)号：US20250006678A1

公开(公告)日：2025-01-02

申请号：US18345437

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Harini Kilambi ,  Kimin Jun ,  Adel A. Elsherbini ,  John Edward Zeug Matthiesen ,  Trianggono Widodo ,  Adita Das ,  Mohit Bhatia ,  Dimitrios Antartis ,  Bhaskar Jyoti Krishnatreya ,  Rajesh Surapaneni ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

公开(公告)号：US20250006653A1

公开(公告)日：2025-01-02

申请号：US18346108

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Bhaskar Jyoti Krishnatreya ,  Francisco Maya ,  Siyan Dong ,  Alveera Gill ,  Tan Nguyen ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.

公开(公告)号：US20240063091A1

公开(公告)日：2024-02-22

申请号：US17891735

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Scot Kellar ,  Yoshihiro Tomita ,  Rajiv Mongia ,  Kimin Jun ,  Shawna Liff ,  Wenhao Li ,  Johanna Swan ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Haris Khan Niazi ,  Jiraporn Seangatith ,  Thomas Sounart

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/473 ,  H01L24/08 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3738 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/182 ,  H01L2924/186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.