公开(公告)号：US20220108182A1

公开(公告)日：2022-04-07

申请号：US17551170

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Todd A. Anderson ,  Shengtian Zhou ,  Javier Turek ,  Celine Lee ,  Justin Gottschlich

IPC: G06N3/08 ,  G06F40/30 ,  G06N3/04

Abstract: Methods and apparatus to train models for program synthesis are disclosed. A disclosed example apparatus includes at least one memory, instructions, and processor circuitry. The processor circuitry is to execute the instructions to sample pairs of programs, the pairs of programs including first programs and second programs, the first programs including natural language descriptions and second programs, calculate program similarity scores corresponding to the pairs of programs, and train a model based on entries corresponding to ones of the pairs of programs, at least one of the entries including a corresponding one of the natural language descriptions with a paired one of the second programs, and a corresponding one of the program similarity scores.

公开(公告)号：US20190325316A1

公开(公告)日：2019-10-24

申请号：US16457133

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Todd A. Anderson ,  Mohammad Mejbah Ul Alam ,  Shengtian Zhou ,  Justin Gottschlich

IPC: G06N3/08 ,  G16H20/30

Abstract: Example apparatus and methods for program synthesis using genetic algorithms are disclosed herein. An example apparatus includes a program length predictor to predict a length of a first program by executing a first neural network model, a program generator to generate a candidate program having a length corresponding to the predicted length, a candidate program analyzer to generate a fitness score for the candidate program by executing a second neural network model and to identify the first candidate program for use in a breeding operation relative a second candidate program based on the fitness score, and a genetic program generator to perform the breeding operation with at least one of the first candidate program or the second candidate program to generate an evolved candidate program.

公开(公告)号：US10310826B2

公开(公告)日：2019-06-04

申请号：US14946200

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Jongsoo Park ,  Todd A. Anderson

IPC: G06F8/41 ,  G06F17/16

Abstract: Technologies for automatic reordering of sparse matrices include a computing device to determine a distributivity of an expression defined in a code region of a program code. The expression is determined to be distributive if semantics of the expression are unaffected by a reordering of an input/output of the expression. The computing device performs inter-dependent array analysis on the expression to determine one or more clusters of inter-dependent arrays of the expression, wherein each array of a cluster of the one or more clusters is inter-dependent on each other array of the cluster, and performs bi-directional data flow analysis on the code region by iterative backward and forward propagation of reorderable arrays through expressions in the code region based on the one or more clusters of the inter-dependent arrays. The backward propagation is based on a backward transfer function and the forward propagation is based on a forward transfer function.

公开(公告)号：US09690552B2

公开(公告)日：2017-06-27

申请号：US14583657

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Peng Tu ,  Tatiana Shpeisman ,  Hai Liu ,  Todd A. Anderson ,  Youfeng Wu ,  Paul M. Petersen ,  Victor W. Lee ,  P. G. Lowney ,  Arch D. Robison ,  Cheng Wang

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/43 ,  G06F8/31 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/453 ,  G06F8/49 ,  G06F8/54

Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.