公开(公告)号：US09747108B2

公开(公告)日：2017-08-29

申请号：US14671475

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Oren Ben-Kiki ,  Ilan Pardo ,  Arch D. Robison ,  James H. Cownie

IPC: G06F12/10 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/30

CPC classification number: G06F9/3822 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3806 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/46 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/6028

Abstract: A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US09690552B2

公开(公告)日：2017-06-27

申请号：US14583657

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Peng Tu ,  Tatiana Shpeisman ,  Hai Liu ,  Todd A. Anderson ,  Youfeng Wu ,  Paul M. Petersen ,  Victor W. Lee ,  P. G. Lowney ,  Arch D. Robison ,  Cheng Wang

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/43 ,  G06F8/31 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/453 ,  G06F8/49 ,  G06F8/54

Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

公开(公告)号：US10528345B2

公开(公告)日：2020-01-07

申请号：US14671914

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Ilan Pardo ,  Oren Ben-Kiki ,  Arch D. Robison ,  Nadav Chachmon ,  James H. Cownie

IPC: G06F9/30 ,  G06F9/52

Abstract: Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.

公开(公告)号：US09760410B2

公开(公告)日：2017-09-12

申请号：US14568890

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Arch D. Robison

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/522

Abstract: Technologies for multithreaded synchronization including a computing device having a many-core processor. Each processor core includes multiple hardware threads. A hardware thread executed by a processor core enters a synchronization barrier and synchronizes with other hardware threads executed by the same processor core. After synchronization, the hardware thread synchronizes with a source hardware thread that may be executed by a different processor core. The source hardware thread may be assigned using an n-way shuffle of all hardware threads, where n is the number of hardware threads per processor core. The hardware thread resynchronizes with the other hardware threads executed by the same processor core. The hardware thread alternately synchronizes with the source hardware thread and the other hardware threads executed by the same processor core until all hardware threads have synchronized. The computing device may reduce a Boolean value over the synchronization barrier. Other embodiments are described and claimed.

公开(公告)号：US20160283245A1

公开(公告)日：2016-09-29

申请号：US14671475

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Oren Ben-Kiki ,  Ilan Pardo ,  Arch D. Robison ,  James H. Cownie

IPC: G06F9/38 ,  G06F12/08 ,  G11C7/10

CPC classification number: G06F9/3822 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3806 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/46 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/6028

Abstract: A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.

Abstract translation: 一方面的处理器包括多个处理器元件和第一处理器元件。 第一处理器元件可以执行软件线程的用户级叉指令。 第一处理器元件可以包括用于解码用户级叉指令的解码器。 用户级fork指令至少指示一个指令地址。 第一处理器元件还可以包括用户级线程分支模块。 用户级叉模块响应于被解码的用户级fork指令，可以配置多个处理器元件中的每一个并行执行指令。 公开了其他处理器，方法，系统和指令。