公开(公告)号：US20230161613A1

公开(公告)日：2023-05-25

申请号：US17535458

申请日：2021-11-24

Applicant: Intel Corporation

Inventor： Jaishankar Rajendran ,  Jun Nakajima ,  Prashant Kodali ,  Karthik Varadarajan ,  Premanand Sakarda ,  Zhiyuan Lv ,  Vaibhav Shankar

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/45545

Abstract: Techniques and mechanisms for a host passthrough to be performed based on the execution of a hardware identification instruction with a virtual machine (VM). In an embodiment, a hypervisor process sets a value of a control parameter corresponding to a resource of the VM. The control parameter indicates whether the VM resource is authorized to avail of a host passthrough functionality of a processor which executes the hypervisor process. The control parameter is evaluated, based on a central processing unit identification (CPUID) instruction of a guest operating system which is executed with the VM, to determine whether the CPUID instruction is to result in a host passthrough or a VM exit. In another embodiment, a shared memory resource is searched to determine whether execution of the CPUID instruction is to retrieve information without the use of either the host passthrough or the VM exit.

公开(公告)号：US20210303053A1

公开(公告)日：2021-09-30

申请号：US16833131

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Christopher Lake ,  Vaibhav Shankar ,  Prashant Kodali

IPC: G06F1/3206 ,  G06F1/3296

Abstract: Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.

公开(公告)号：US11340683B2

公开(公告)日：2022-05-24

申请号：US16833131

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Christopher Lake ,  Vaibhav Shankar ,  Prashant Kodali

IPC: G06F1/3206 ,  G06F1/3296

Abstract: Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.