公开(公告)号：US20220391007A1

公开(公告)日：2022-12-08

申请号：US17886366

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  George VERGIS ,  Stephen P. CHRISTIANSON ,  Ankita TIWARI ,  Virendra Vikramsinh ADSURE

IPC: G06F1/3234 ,  H01L23/14

Abstract: Apparatus, assemblies, and platforms employing modular power voltage regulator (VR) modules to provide power to memory modules. A power VR module includes VR circuitry integrated on or coupled to a substrate with wiring coupling the VR circuitry to connector elements in first and second connector means. An assembly further includes a pair of memory modules (e.g., DDR) that are coupled to a power VR module via mating connector means. The connector means may be coupled using a Compression Mount Technology (CMT) connector disposed between arrays of CMT contact pads on the power VR module and the memory modules, or may comprise BGAs, PGAs, and LGAs. The power VR module receives one or more input voltages via one or both memory module and provide various output voltages to each of the memory modules to power memory devices and other circuitry on those modules.

公开(公告)号：US20210325956A1

公开(公告)日：2021-10-21

申请号：US17359403

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Virendra Vikramsinh ADSURE ,  Chia-Hung S. KUO ,  Robert J. ROYER, JR. ,  Deepak GANDIGA SHIVAKUMAR

IPC: G06F1/3293

Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.