公开(公告)号：US12079138B2

公开(公告)日：2024-09-03

申请号：US17892879

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/355 ,  G06F9/455

CPC classification number: G06F12/10 ,  G06F9/30174 ,  G06F9/355 ,  G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

公开(公告)号：US11422943B2

公开(公告)日：2022-08-23

申请号：US15553853

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

公开(公告)号：US20220405210A1

公开(公告)日：2022-12-22

申请号：US17892879

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.