公开(公告)号：US20220405210A1

公开(公告)日：2022-12-22

申请号：US17892879

申请日：2022-08-22

申请人： Intel Corporation

发明人： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC分类号： G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

摘要： An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

公开(公告)号：US20240320047A1

公开(公告)日：2024-09-26

申请号：US18575147

申请日：2022-02-24

申请人： Intel Corporation

发明人： Jianhui Li ,  Zhennan Qin ,  Jiong Gong ,  Jingze Cui ,  Yijie Mei ,  Yunfei Song

IPC分类号： G06F9/50

CPC分类号： G06F9/5027

摘要： Systems, apparatuses and methods may provide for technology that identifies a data layout associated with input tensors and output tensors, generates a micro-kernel based at least in part on the data layout, and generates a nested outer loop for a kernel, wherein the micro-kernel performs one or more subtasks associated with a task represented by the kernel. The technology also includes micro-kernel code caches, fused kernel generators and cyclic dependence free graph partitioning for deep learning workloads.

公开(公告)号：US20180173545A1

公开(公告)日：2018-06-21

申请号：US15843822

申请日：2017-12-15

申请人： Intel Corporation

发明人： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

IPC分类号： G06F9/455 ,  G06F9/445

CPC分类号： G06F9/455 ,  G06F9/44521 ,  G06F9/4552

摘要： Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

公开(公告)号：US09996892B2

公开(公告)日：2018-06-12

申请号：US14780440

申请日：2014-11-21

申请人： INTEL CORPORATION

发明人： Li Yin ,  Jianhui Li

IPC分类号： G06T15/00 ,  G06T1/20 ,  G06F9/455 ,  G06F9/54 ,  H04N21/443 ,  G06F9/30 ,  G06F9/46

CPC分类号： G06T1/20 ,  G06F9/30145 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F9/46 ,  G06F9/541 ,  G06T15/005 ,  H04N21/4431

摘要： An apparatus and method are described for improving the efficiency of graphics operations in a virtual execution environment. For example, one embodiment of a system comprises: a classification module to detect graphics application programming interface (API) calls in a guest execution environment and responsively classify the graphics API calls as originating from an application or a system component; the classification module to associate information with each of the graphics API calls to indicate whether each of the graphics API calls originated from the application or from the system component; and an enhanced graphics API translator (EGAT) to translate the graphics API calls to a format executable in a host execution environment, the EGAT to identify each of the API calls as originating from the application or the system component using the information associated with the graphics API calls by the classification module, the EGAT comprising: a first translation sequence to translate the graphics API calls to a first set of translated graphics API calls if the graphics API calls originated from the application; and a second translation sequence to translate the graphics API calls to a second set of translated graphics API calls if the graphics API calls originated from the system component, the first set of translated graphics API calls being different from the second set of translated graphics API calls.

公开(公告)号：US10761867B2

公开(公告)日：2020-09-01

申请号：US15843822

申请日：2017-12-15

申请人： Intel Corporation

发明人： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

IPC分类号： G06G7/48 ,  G06F9/455 ,  G06F9/445

摘要： Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

公开(公告)号：US09928067B2

公开(公告)日：2018-03-27

申请号：US13976359

申请日：2012-09-21

申请人： Intel Corporation

发明人： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Jane Chen ,  Gang Wang ,  Yi Qian ,  Huifeng Gu

IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/38 ,  G06F9/455

CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30072 ,  G06F9/3861 ,  G06F9/4552

摘要： Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

公开(公告)号：US09910721B2

公开(公告)日：2018-03-06

申请号：US14777065

申请日：2014-12-09

申请人： Intel Corporation

发明人： Yong Wu ,  Xiao Dong Lin ,  Yihua Jin ,  Xueliang Zhong ,  Jianhui Li

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F9/45 ,  G06F9/30 ,  G06F9/455

CPC分类号： G06F9/541 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/4552 ,  G06F9/45533

摘要： Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220253488A1

公开(公告)日：2022-08-11

申请号：US17630461

申请日：2019-09-27

申请人： Intel Corporation

发明人： Jianhui Li ,  Yong Wu ,  Ningxin Hu ,  Yiqiang Li ,  Yuanke Luo

IPC分类号： G06F16/954 ,  G06N3/04 ,  G06N3/08

摘要： Methods, apparatus, systems, and articles of manufacture to process a machine learning model in a web-browser environment are disclosed. An example apparatus includes a graph builder to accumulate machine learning operations as a graph. A tensor manager is to, in response to a request to access a tensor that is not yet available and associated with the machine learning operations, identify the graph based on the tensor. A graph cache manager is to determine whether a condensed graph corresponding to the identified graph is available. A graph condenser is to, in response to the graph cache manager determining that the condensed graph is not available, generate the condensed graph. A graph executor is to execute the condensed graph to create the tensor. The tensor manager is to provide the tensor as a response to the request to access the tensor.

公开(公告)号：US10152335B2

公开(公告)日：2018-12-11

申请号：US15024143

申请日：2013-11-15

申请人： Intel Corporation

发明人： Yihua Jin ,  Jianhui Li ,  Tingtao Li ,  Xiaodong Lin

IPC分类号： G06F9/445 ,  G06F9/44 ,  G06F3/0488 ,  G06F9/451 ,  G06F9/455

摘要： Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.

公开(公告)号：US09753787B2

公开(公告)日：2017-09-05

申请号：US14724394

申请日：2015-05-28

申请人： Intel Corporation

发明人： Yihua Jin ,  Xiao Dong Lin ,  Yong Wu ,  Jianhui Li ,  Xueliang Zhong

IPC分类号： G06F9/54 ,  G06F12/0842 ,  G06F9/46 ,  G06F12/02

CPC分类号： G06F9/54 ,  G06F9/461 ,  G06F9/466 ,  G06F12/0284 ,  G06F12/0842 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/62

摘要： Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.