公开(公告)号：US10095520B2

公开(公告)日：2018-10-09

申请号：US15194558

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Zhen Fang ,  Xiaowei Jiang ,  Srihari Makineni ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F13/24 ,  G06F9/48

Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

公开(公告)号：US09753732B2

公开(公告)日：2017-09-05

申请号：US15175427

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Xiaowei Jiang ,  Srihari Makineni ,  Zhen Fang ,  Dmitri Pavlov ,  Ravi Iyer

IPC: G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

公开(公告)号：US20160283244A1

公开(公告)日：2016-09-29

申请号：US15175427

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Xiaowei Jiang ,  Srihari Makineni ,  Zhen Fang ,  Dmitri Pavlov ,  Ravi Iyer

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

Abstract translation: 根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。 另外，分支预测单元也可以不包括分支预测器。 此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。 在某些情况下，这种布置减少了分支预测单元的面积以及功耗。