公开(公告)号：US20250006806A1

公开(公告)日：2025-01-02

申请号：US18346087

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Alexander Badmaev ,  Zhiyi Chen ,  Debaleena Nandi ,  Tahir Ghani

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.