公开(公告)号：US09974024B2

公开(公告)日：2018-05-15

申请号：US15077197

申请日：2016-03-22

Applicant: Intel IP Corporation

Inventor： Michael Speth ,  Armin Haeutle ,  Frank Huertgen ,  Biswajit Dey ,  Markus Jordan

IPC: H04W52/02

CPC classification number: H04W52/0245 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1262

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

公开(公告)号：US20160316434A1

公开(公告)日：2016-10-27

申请号：US15077197

申请日：2016-03-22

Applicant: Intel IP Corporation

Inventor： Michael Speth ,  Armin Haeutle ,  Frank Huertgen ,  Biswajit Dey ,  Markus Jordan

IPC: H04W52/02 ,  H04W24/08

CPC classification number: H04W52/0245 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1262

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

Abstract translation: 根据示例的电路包括被配置为接收包括数据流的信号的接收器电路，所述数据流包括至少一个数据块，所述至少一个数据块的块包括至少两个子块， 所述块的有效载荷被冗余地编码在所述至少两个子块中，并且所述块的所述至少两个子块在所述块内随时间一致地排列。 该电路还包括控制电路，该控制电路被配置为当满足该允许条件时，在该块的至少两个子块中的至少一个子块的至少一部分期间将接收器电路切换为不准备接收状态 。