公开(公告)号：US06521493B1

公开(公告)日：2003-02-18

申请号：US09574891

申请日：2000-05-19

申请人： Johann Alsmeier ,  Giuseppe LaRosa ,  Joseph Lukaitis ,  Rajesh Rengarajan

发明人： Johann Alsmeier ,  Giuseppe LaRosa ,  Joseph Lukaitis ,  Rajesh Rengarajan

IPC分类号： H01L218238

CPC分类号： H01L21/76229 ,  H01L21/76237

摘要： A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

摘要翻译： 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 在形成氧化物衬垫之后，掩模半导体衬底的第一区域，使第二区域暴露。 在第一区域中将形成N型器件，并且在第二区域中将形成p型器件。 然后可以将N型离子注入到第二区域中的沟槽的侧壁中。 剥离掩模，并且可以以常规方式进行半导体器件的形成。 n型离子优选仅被注入形成PMOSFET的侧壁。

公开(公告)号：US06762966B1

公开(公告)日：2004-07-13

申请号：US10338928

申请日：2003-01-08

申请人： Giuseppe LaRosa ,  Alvin W. Strong

发明人： Giuseppe LaRosa ,  Alvin W. Strong

IPC分类号： G11C2900

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C2029/5002

摘要： An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.

摘要翻译： 描述了在现实操作环境中量化DRAM单元的晶体管电荷转移性能和电荷保持能力的片上电路和测试方法。 可以扩展该方法和电路以评估由于在电荷转移期间以及在操作或老化条件下储存期间激活的MOSFET损耗机制，电池转移装置的老化。 片上电路强制并感测到单个DRAM存储电容器的电压，允许脉冲测试方法表征各个存储电容器电荷泄漏率，并量化DRAM单元中位线和存储电容器之间的电荷转移速率。

公开(公告)号：US06867472B2

公开(公告)日：2005-03-15

申请号：US10338517

申请日：2003-01-08

申请人： Rajesh Renegarajan ,  Giuseppe LaRosa ,  Mark Dellow

发明人： Rajesh Renegarajan ,  Giuseppe LaRosa ,  Mark Dellow

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/00 ,  H01L29/78

CPC分类号： H01L21/28123 ,  H01L27/10873 ,  H01L29/7838

摘要： A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a surface of the substrate to a first depth. A buried conductive channel layer is formed within the transistor junction between the surface of the substrate and the first depth. The buried conductive channel layer has a peak conduction depth, which is different from a depth of the area susceptible to hot carrier effects.

摘要翻译： 半导体器件包括形成在与隔离区相邻的衬底中的晶体管结。 晶体管结和隔离区之间的区域包括易受热载流子影响的区域。 晶体管结从衬底的表面延伸到第一深度。 掩埋的导电沟道层形成在衬底的表面和第一深度之间的晶体管结内。 掩埋导电沟道层具有峰值导通深度，其不同于易受热载流子影响的区域的深度。