公开(公告)号：US07765450B2

公开(公告)日：2010-07-27

申请号：US11256211

申请日：2005-10-20

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G06F11/00

CPC分类号： G01R31/318314 ,  G01R31/31707

摘要： As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

摘要翻译： 如本文所述，电路测试算法或其部分可以以分布式方式执行，使得它们的执行可以通过处理器的网络。 在一个方面，通过这种分布式执行获得的结果被确保与通过以非分布式执行它们将获得的结果一致。 因此，在一个方面，算法或其部分必须被分配。 算法或其部分通过将其随机数生成与彼此独立地分离来实现。 该隔离也适用于与相同算法的不同调用实例相关联的任何随机数生成。 在一个方面，通过确保用于算法或其部分的随机数序列的计算不依赖于为其他人计算的随机数序列或相同算法的呼叫实例之间的计算来实现隔离。

公开(公告)号：US20080320352A1

公开(公告)日：2008-12-25

申请号：US12197892

申请日：2008-08-25

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/3181

CPC分类号： G01R31/318314 ,  G01R31/31707

摘要： As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

摘要翻译： 如本文所述，电路测试算法或其部分可以以分布式方式执行，使得它们的执行可以通过处理器的网络。 在一个方面，通过这种分布式执行获得的结果被确保与通过以非分布式执行它们将获得的结果一致。 因此，在一个方面，算法或其部分必须被分配。 算法或其部分通过将其随机数生成与彼此独立地分离来实现。 该隔离也适用于与相同算法的不同调用实例相关联的任何随机数生成。 在一个方面，通过确保用于算法或其部分的随机数序列的计算不依赖于为其他人计算的随机数序列或相同算法的呼叫实例之间的计算来实现隔离。

公开(公告)号：US20070094556A1

公开(公告)日：2007-04-26

申请号：US11255777

申请日：2005-10-20

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/28

CPC分类号： G01R31/318314

摘要： Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network comprises a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. To ensure consistency between the performance of algorithms, or portions thereof, in a distributed manner and a non-distributed manner, the order of processing results from execution is according to some pre-determined order, or according to the order in which the results would have been processed during a non-distributed (e.g., sequential) execution, for instance. For algorithms that are highly sequential in nature, portions of algorithms can be modified to delay the need for dependent results between algorithm portions by creating a rolling window of independent tasks that is iterated.

摘要翻译： 这里描述了用于分布式执行电路测试算法或其部分的方法和系统。 分布式处理可以加快处理速度。 彼此独立的算法或算法的部分可以以多个处理器的网络上的非连续方式（例如，并行）来执行。 该网络包括一个控制处理器，可以将任务分配给其他处理器，并自行执行某些任务。 依赖算法或其部分可以以顺序方式在控制处理器或受控处理器之一上执行。 为了确保算法或其部分的分布式和非分布式方式的性能之间的一致性，来自执行的处理结果的顺序是根据一些预定的顺序，或者根据结果将按顺序 例如，在非分布（例如，顺序）执行期间已被处理。 对于本质上具有高度连续性的算法，可以修改算法的部分，以通过创建迭代的独立任务的滚动窗口来延迟对算法部分之间的依赖结果的需求。

公开(公告)号：US07386778B2

公开(公告)日：2008-06-10

申请号：US11255777

申请日：2005-10-20

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/28

CPC分类号： G01R31/318314

摘要： Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner.

摘要翻译： 这里描述了用于分布式执行电路测试算法或其部分的方法和系统。 分布式处理可以加快处理速度。 彼此独立的算法或算法的部分可以以多个处理器的网络上的非连续方式（例如，并行）来执行。 该网络包括一个控制处理器，可以将任务分配给其他处理器，并自行执行某些任务。 依赖算法或其部分可以以顺序方式在控制处理器或受控处理器之一上执行。

公开(公告)号：US20080216076A1

公开(公告)日：2008-09-04

申请号：US12117701

申请日：2008-05-08

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G06F9/46

CPC分类号： G01R31/318314

摘要： Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network comprises a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. To ensure consistency between the performance of algorithms, or portions thereof, in a distributed manner and a non-distributed manner, the order of processing results from execution is according to some pre-determined order, or according to the order in which the results would have been processed during a non-distributed (e.g., sequential) execution, for instance. For algorithms that are highly sequential in nature, portions of algorithms can be modified to delay the need for dependent results between algorithm portions by creating a rolling window of independent tasks that is iterated.

摘要翻译： 这里描述了用于分布式执行电路测试算法或其部分的方法和系统。 分布式处理可以加快处理速度。 彼此独立的算法或算法的部分可以以多个处理器的网络上的非连续方式（例如，并行）来执行。 该网络包括一个控制处理器，可以将任务分配给其他处理器，并自行执行某些任务。 依赖算法或其部分可以以顺序方式在控制处理器或受控处理器之一上执行。 为了确保算法或其部分的分布式和非分布式方式的性能之间的一致性，来自执行的处理结果的顺序是根据一些预定的顺序，或者根据结果将按顺序 例如，在非分布（例如，顺序）执行期间已被处理。 对于本质上具有高度连续性的算法，可以修改算法的部分，以通过创建迭代的独立任务的滚动窗口来延迟对算法部分之间的依赖结果的需求。

公开(公告)号：US20070094561A1

公开(公告)日：2007-04-26

申请号：US11256211

申请日：2005-10-20

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/28

CPC分类号： G01R31/318314 ,  G01R31/31707

摘要： As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

摘要翻译： 如本文所述，电路测试算法或其部分可以以分布式方式执行，使得它们的执行可以通过处理器的网络。 在一个方面，通过这种分布式执行获得的结果被确保与通过以非分布式执行它们将获得的结果一致。 因此，在一个方面，算法或其部分必须被分配。 算法或其部分通过将其随机数生成与彼此独立地分离来实现。 该隔离也适用于与相同算法的不同调用实例相关联的任何随机数生成。 在一个方面，通过确保用于算法或其部分的随机数序列的计算不依赖于为其他人计算的随机数序列或相同算法的呼叫实例之间的计算来实现隔离。

公开(公告)号：US07669101B2

公开(公告)日：2010-02-23

申请号：US12117701

申请日：2008-05-08

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/28

CPC分类号： G01R31/318314

摘要： Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. For algorithms that are highly sequential in nature, portions of algorithms can be modified to delay the need for dependent results between algorithm portions by creating a rolling window of independent tasks that is iterated.

摘要翻译： 这里描述了用于分布式执行电路测试算法或其部分的方法和系统。 分布式处理可以加快处理速度。 彼此独立的算法或算法的部分可以以多个处理器的网络上的非连续方式（例如，并行）来执行。 该网络包括一个控制处理器，可以将任务分配给其他处理器，并自行执行某些任务。 依赖算法或其部分可以以顺序方式在控制处理器或受控处理器之一上执行。 对于本质上具有高度连续性的算法，可以修改算法的部分，以通过创建迭代的独立任务的滚动窗口来延迟对算法部分之间的依赖结果的需求。

公开(公告)号：US08051352B2

公开(公告)日：2011-11-01

申请号：US11796374

申请日：2007-04-27

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

摘要翻译： 这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。 在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。 定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。 为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。 实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

公开(公告)号：US10509073B2

公开(公告)日：2019-12-17

申请号：US15664169

申请日：2017-07-31

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G01R31/3183 ,  G01R31/3177 ,  G06F17/50

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

公开(公告)号：US08560906B2

公开(公告)日：2013-10-15

申请号：US13285899

申请日：2011-10-31

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.