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    System and method for access control of a plurality of instruments embedded in a semiconductor device
    1.
    发明授权
    System and method for access control of a plurality of instruments embedded in a semiconductor device 有权

    公开(公告)号：US12111356B2

    公开(公告)日：2024-10-08

    申请号：US17766849

    申请日：2020-10-09

    申请人： Erik Larsson

    发明人： Erik Larsson

    IPC分类号： G01R31/3185 ,  G01R31/317 ,  G01R31/3183

    CPC分类号： G01R31/318555 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/318558 ,  G01R31/318314

    摘要： A system for accessing a plurality of instruments embedded in a semiconductor device includes a hardware interface and a test controller for testing the semiconductor device or generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments. The test controller is configured to perform the steps of: testing at least one functionality of each of the plurality of instruments, thereby receiving a fault status of each of the plurality of instruments; and based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration.

    Multi-die debug stop clock trigger
    3.
    发明授权
    Multi-die debug stop clock trigger 有权

    公开(公告)号：US11946969B2

    公开(公告)日：2024-04-02

    申请号：US17880507

    申请日：2022-08-03

    申请人： Apple Inc.

    发明人： Charles J. Fleckenstein ,  Tal Lazmi ,  Ori Isachar

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319

    CPC分类号： G01R31/31705 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318314 ,  G01R31/31924

    摘要： Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

    SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS EMBEDDED IN A SEMICONDUCTOR DEVICE
    4.
    发明公开
    SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS EMBEDDED IN A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240061041A1

    公开(公告)日：2024-02-22

    申请号：US17766849

    申请日：2020-10-09

    申请人： Erik Larsson

    发明人： Erik Larsson

    IPC分类号： G01R31/3185 ,  G01R31/317

    CPC分类号： G01R31/318555 ,  G01R31/31723 ,  G01R31/318558 ,  G01R31/318314

    摘要： A system for accessing a plurality of instruments embedded in a semiconductor device includes a hardware interface and a test controller for testing the semiconductor device or generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments. The test controller is configured to perform the steps of: testing at least one functionality of each of the plurality of instruments, thereby receiving a fault status of each of the plurality of instruments; and based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration.

    LOGIC ANALYZER AND PROBE THEREOF
    7.
    发明申请
    LOGIC ANALYZER AND PROBE THEREOF 审中-公开

    公开(公告)号：US20180120377A1

    公开(公告)日：2018-05-03

    申请号：US15326440

    申请日：2015-05-18

    申请人： ZEROPLUS TECHNOLOGY CO., LTD.

    发明人： CHIU-HAO CHENG

    IPC分类号： G01R31/3177 ,  G01R31/319 ,  G01R31/3183 ,  G01R31/28

    CPC分类号： G01R31/3177 ,  G01R1/06788 ,  G01R13/02 ,  G01R31/2808 ,  G01R31/318314 ,  G01R31/31905

    摘要： A logic analyzer includes a probe, a first transmission line, a display, a second transmission line, and a processing unit. The probe is adapted to abut against a DUT to retrieve digital signals therefrom. The first transmission line is electrically connected to the probe. The display is provided on the probe. The second transmission line is electrically connected to the display. The processing unit is electrically connected to the first transmission line and the second transmission line, and is adapted to be electrically connected to a computer. The digital signal retrieved by the probe would be transmitted to the processing unit through the first transmission line to be analyzed therein. After completing the analysis, an analysis result would be transmitted to the computer for display. Meanwhile, a part of the analysis result is transmitted to the display through the second transmission line to be displayed thereon.

    Low Cost Design for Test Architecture
    9.
    发明申请
    Low Cost Design for Test Architecture 审中-公开

    公开(公告)号：US20170193154A1

    公开(公告)日：2017-07-06

    申请号：US15397567

    申请日：2017-01-03

    申请人： Chinsong Sul

    发明人： Chinsong Sul

    IPC分类号： G06F17/50

    CPC分类号： G01R31/318364 ,  G01R31/31704 ,  G01R31/318314

    摘要： A Design-for-testability method based on composition of test patterns copes with increasing test complexity and cost metric of a large system. System-level structural test patterns from test patterns of constituent subsystems, cores and design IPs are constructed without requiring their design netlists. The delivered test patterns can be utilized 100% in the testing of system. The system-level test pattern is delivered to the device under test, the subsystem test patterns can be scheduled and applied continuously without being interleaved by test deliveries until all of the subsystem test patterns are exercised. Absence of design netlist requirement allows uniform integration of external and internal IPs regardless of availability of test isolation logic or design details. Concurrent test of constituents and their mutual independence in scan operations allows implicit distribution of test protocol signals such as scan enable (SE) and the scan clocks. The method enables at-speed testing of memory shadow logic.

    TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING LATENCY DETECTION
    10.
    发明申请
    TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING LATENCY DETECTION 有权
    测试建筑物，系统，设备和方法，包括延迟检测

    公开(公告)号：US20160139202A1

    公开(公告)日：2016-05-19

    申请号：US14672025

    申请日：2015-03-27

    申请人： XPLIANT, INC.

    发明人： Saurin Patel ,  Nimalan Siva ,  Keqin Kenneth Han

    IPC分类号： G01R31/3177 ,  G01R31/317

    CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318314 ,  G06F11/2273 ,  G06F11/261 ,  G06F11/263 ,  G06F11/364 ,  G06F17/5009 ,  G06F17/5081 ,  H04L43/14 ,  H04L43/50

    摘要： A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

    摘要翻译： 用于测试被测设备（DUT）的测试台，其中测试台具有验证环境，其包括DUT需要从其接收输入和/或传输输出的每个接口的参考模型，记分板和定制代理。 测试平台系统能够由测试平台构建器生成，该测试平台构建器自动创建记分板，参考模型，调度程序和通用代理，包括通用驱动程序，回送端口，顺控程序和/或每个界面的通用监视器，然后自动定制通用代理 基于其对应的接口，使代理符合DUT的接口要求。