公开(公告)号：US20220262422A1

公开(公告)日：2022-08-18

申请号：US17470802

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Marina YAMAGUCHI ,  Kensuke OTA ,  Kazuhiko YAMAMOTO ,  Masumi SAITOH

IPC: G11C11/22

Abstract: A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.

公开(公告)号：US20210091095A1

公开(公告)日：2021-03-25

申请号：US16806253

申请日：2020-03-02

Applicant: Kioxia Corporation

Inventor： Tsunehiro INO ,  Kazuhiko YAMAMOTO

IPC: H01L27/1159 ,  H01L27/11597

Abstract: According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.

公开(公告)号：US20210376236A1

公开(公告)日：2021-12-02

申请号：US17201356

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Bairu YAN ,  Yoshiki KAMATA ,  Kazuhiko YAMAMOTO

IPC: H01L45/00 ,  H01L27/24

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a resistive layer provided between the first electrode and the second electrode, containing at least one of antimony (Sb) and bismuth (Bi) as a first element, and tellurium (Te) as a second element, and having a variable resistance value. The resistive layer includes a first layer having a hexagonal crystal structure containing the first element and the second element. The first layer contains a group 14 element as a third element.

公开(公告)号：US20210296400A1

公开(公告)日：2021-09-23

申请号：US17125126

申请日：2020-12-17

Applicant: Kioxia Corporation

Inventor： Tsunehiro INO ,  Yukihiro NOMURA ,  Kazuhiko YAMAMOTO ,  Koji USUDA

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

公开(公告)号：US20210083003A1

公开(公告)日：2021-03-18

申请号：US16803863

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiko YAMAMOTO

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a third wiring extending in the second direction and spaced from the second wiring in the first direction. An insulating layer includes a first portion between the second wiring and the third wiring, and a second portion protruding from the first portion in a third direction. A chalcogenide layer is between the first wiring and the second wiring, the first wiring and the third wiring, and also the first wiring and the insulating layer. The chalcogenide layer includes a first layer portion, a second layer portion, and a third layer portion. A concentration of a first element in the third layer portion is higher than that in the first and second layer portions.