MINIMIZING TWO-STEP AND HARD STATE TRANSITIONS IN MULTI-LEVEL STT_MRAM DEVICES

    公开(公告)号:US20190103150A1

    公开(公告)日:2019-04-04

    申请号:US15724075

    申请日:2017-10-03

    CPC classification number: G11C11/1675 G11C7/1006 G11C11/1653 G11C11/5607

    Abstract: Data is stored in a multi-level MRAM (MLC MRAM) cell in a manner that reduces transition states that require high energy. A new data block is received, and the new data block is divided into one or more sub-groups of bits, with each sub-group comprising at least two bits. Each sub-group is assigned data bit locations in a memory store. The received bits are compared with sub-groups present at the data bit locations to determine subgroups of hot bits. For each subgroup of hot bits, an encoding flag value is determined by XORing their most significant bits. The most significant bits of each subgroup of hot bits are complemented and the encoding flag is SET. A data block is generated to establish a data group for each subgroup of hot bits including the subgroup of hot bits and the encoding flag for that subgroup.

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