中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

2 records (took 0.013 seconds)

    DUAL CONTROL ANALOG DELAY ELEMENT
    1.
    发明申请
    DUAL CONTROL ANALOG DELAY ELEMENT 失效
    双控模拟延迟元件

    公开(公告)号：US20080036500A1

    公开(公告)日：2008-02-14

    申请号：US11833559

    申请日：2007-08-03

    Applicant: Ki-Jun LEE ,  Gurpreet BHULLAR

    Inventor： Ki-Jun LEE ,  Gurpreet BHULLAR

    IPC: H03K19/00

    CPC classification number: H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

    Abstract: An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

    Abstract translation: 用于延迟输入时钟信号以产生输出时钟信号的模拟延迟元件。 模拟延迟元件包括用于接收输入时钟信号并响应于第一偏置电压提供中间时钟信号的延迟电路。 电流镜放大器响应于中间时钟信号在第一电流分支中产生第一电流，并响应于第一电流和第二偏置电压在第二电流分支中产生第二电流。 第二电流分支具有用于提供具有与延迟的中间时钟信号逻辑电平相对应的逻辑电平的输出时钟信号的输出节点。

Patent Agency Ranking