公开(公告)号：US12101092B2

公开(公告)日：2024-09-24

申请号：US18228502

申请日：2023-07-31

Applicant: EFINIX, INC.

Inventor： Marcel Gort

IPC: H03K5/159 ,  H03K5/133 ,  H03K19/17736 ,  H03K5/00

CPC classification number: H03K5/133 ,  H03K19/1774 ,  H03K19/17744 ,  H03K2005/00019

Abstract: Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

公开(公告)号：US12088304B2

公开(公告)日：2024-09-10

申请号：US17968339

申请日：2022-10-18

Applicant: Magnachip Mixed-Signal, Ltd.

Inventor： Chelho Chung ,  Gilsung Roh

IPC: H03K5/00 ,  H03K5/1252 ,  H03K5/133 ,  H03K5/1536 ,  H03K5/156

CPC classification number: H03K5/133 ,  H03K5/1252 ,  H03K5/1536 ,  H03K5/156

Abstract: A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.

公开(公告)号：US12019573B2

公开(公告)日：2024-06-25

申请号：US18209083

申请日：2023-06-13

Applicant: Uniquify, Inc.

Inventor： Jung Lee ,  Venkat Iyer ,  Brett Murdock

IPC: H03K5/14 ,  G06F13/16 ,  G06F13/362 ,  G06F13/42 ,  G11C8/18 ,  G11C29/02 ,  H03K5/133 ,  H03L7/08 ,  H03L7/081 ,  H03L7/10 ,  H03K5/00

CPC classification number: G06F13/3625 ,  G06F13/1689 ,  G06F13/4256 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/10 ,  H03K2005/00019

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

公开(公告)号：US11973503B2

公开(公告)日：2024-04-30

申请号：US18277098

申请日：2022-09-29

Applicant: Nanjing Prime Semiconductor Co., Ltd.

Inventor： Sunfeng Huang

IPC: H03K5/133 ,  B81B7/00

CPC classification number: H03K5/133 ,  B81B7/0048 ,  B81B2201/0264 ,  B81B2207/03

Abstract: An application specific integrated circuit (ASIC) chip is provided. Stress in various directions can be measured by disposing symmetrical “four-corner+middle” delay chain combinations in three dimensions inside the ASIC chip. Two sensors using the ASIC chip are further provided. In one sensor, a micro-electromechanical system (MEMS) chip is stacked with the ASIC chip. In the other sensor, the MEMS chip and the ASIC chip are symmetrically arranged. After being stacked and symmetrically arranged, the MEMS chip and the ASIC chip have highly consistent stress concentration characteristics, which can calibrate stress in various directions and effectively improve accuracy and temperature stability of the MEMS chip. In addition, an electric toothbrush using the ASIC chip is further provided, which can effectively improve consistency, stability, reliability, sensitivity, and linearity of stress detection, and can more accurately compensate for a temperature drift.

公开(公告)号：US20240127881A1

公开(公告)日：2024-04-18

申请号：US18446508

申请日：2023-08-09

Applicant: Changxin Memory Technologies, Inc.

Inventor： Zequn HUANG ,  Kai Sun

IPC: G11C11/4076 ,  G06F1/08 ,  G06F11/10 ,  H03K5/133

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F11/106 ,  H03K5/133 ,  H03K2005/00058

Abstract: Provided in the embodiments of the present disclosure are a delay control circuit and method, and a semiconductor memory. The delay control circuit includes a clock circuit and a delay circuit. The clock circuit is configured to receive a temperature adjustment signal, and generate a first clock signal according to the temperature adjustment signal; and a clock cycle of the first clock signal is a preset value. The delay circuit is configured to receive the first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal; and a time interval between the target command signal and the initial command signal meets a preset timing condition.

公开(公告)号：US20240113701A1

公开(公告)日：2024-04-04

申请号：US18472335

申请日：2023-09-22

Applicant: LAPIS Technology Co., Ltd.

Inventor： Takuya MATSUMOTO

IPC: H03K5/15 ,  H03K5/133

CPC classification number: H03K5/15073 ,  H03K5/133 ,  H03K2005/00058

Abstract: A semiconductor device configured by bonding a first and a second chip together, including: a first signal output circuit provided at both the first and the second chip and driven by a first drive power; a second signal output circuit provided at both the first and the second chip and driven by a second drive power; a first phase comparison circuit, provided at the first chip, that compares a phase of a first signal and a second signal; a second phase comparison circuit that is provided at the second chip, and that compares a phase of a third signal and a fourth signal; a third phase comparison circuit, provided at the first chip, that compares a phase of a fifth signal and a sixth signal; and a fourth phase comparison circuit, provided at the second chip, that compares a phase of a seventh signal and an eighth signal.

公开(公告)号：US20230420030A1

公开(公告)日：2023-12-28

申请号：US17846967

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Fujiwara ,  Kevin G. Werhane ,  Jason M. Johnson ,  Daniel S. Miller

IPC: G11C11/4076 ,  H03K5/133 ,  G11C29/54

CPC classification number: G11C11/4076 ,  H03K5/133 ,  G11C29/54

Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.

公开(公告)号：US20230370070A1

公开(公告)日：2023-11-16

申请号：US18245013

申请日：2021-08-12

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： MIHO AKAGI ,  YOHTARO YASU

IPC: H03L7/081 ,  H03K5/135 ,  H03K5/133 ,  G01S17/894

CPC classification number: H03L7/0814 ,  H03K5/135 ,  H03K5/133 ,  G01S17/894

Abstract: A DLL circuit (110) includes a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stop circuit (116). The phase delay circuit (114) generates a plurality of delayed signals having different phases according to a clock signal. The selection circuit (115) selects one of the plurality of delayed signals as an output signal according to a setting signal. The detection circuit (117) detects a timing of switching the setting signal. The clock stop circuit (116) stops input of the clock signal to the phase delay circuit (114) for a predetermined period including the timing detected by the detection circuit (117).

公开(公告)号：US11757439B2

公开(公告)日：2023-09-12

申请号：US17584025

申请日：2022-01-25

Applicant: EFINIX, INC.

Inventor： Marcel Gort

IPC: H03K5/159 ,  H03K5/133 ,  H03K19/17736 ,  H03K5/00

CPC classification number: H03K5/133 ,  H03K19/1774 ,  H03K19/17744 ,  H03K2005/00019

Abstract: Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element.

公开(公告)号：US20230283269A1

公开(公告)日：2023-09-07

申请号：US17968339

申请日：2022-10-18

Applicant: Magnachip Semiconductor, Ltd.

Inventor： Chelho CHUNG ,  Gilsung ROH

IPC: H03K5/133

CPC classification number: H03K5/133

Abstract: A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.