公开(公告)号：US20120007653A1

公开(公告)日：2012-01-12

申请号：US13180064

申请日：2011-07-11

申请人： Kyo-Jin CHOO ,  Yu-Jin PARK ,  Yong LIM

发明人： Kyo-Jin CHOO ,  Yu-Jin PARK ,  Yong LIM

IPC分类号： H03K17/00

CPC分类号： H03M9/00 ,  H03K5/15093

摘要： A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain.

摘要翻译： 数据传输装置包括控制单元和延迟链单元。 控制单元通过第n个控制信号输出第一控制信号，其中n是自然数。 延迟链单元包括通过第n个开关元件的第一开关元件。 开关元件通过第n个数据信号接收第一数据信号，并且分别基于第一至第N控制信号对第一至第n数据信号执行流水线操作，以将流水线数据信号作为至少一个数据流输出。 开关元件彼此连接以形成至少一个数据延迟链。

公开(公告)号：US20120113286A1

公开(公告)日：2012-05-10

申请号：US13270968

申请日：2011-10-11

申请人： Seung-Hyun LIM ,  Kwi-Sung YOO ,  Kyoung-Min KOH ,  Yu-Jin PARK ,  Chi-Ho HWANG ,  Yong LIM

发明人： Seung-Hyun LIM ,  Kwi-Sung YOO ,  Kyoung-Min KOH ,  Yu-Jin PARK ,  Chi-Ho HWANG ,  Yong LIM

IPC分类号： H04N5/228 ,  H03M1/12

CPC分类号： H03M1/144 ,  H03M1/56 ,  H04N5/378

摘要： An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

摘要翻译： 模数转换器（ADC）可以包括多输入比较单元，其被配置为比较来自图像传感器的像素电压，包括在粗略操作模式期间修改的阶梯电压的比较电压和包括斜坡电压的斜坡电压 在精细操作模式下彼此修改，以提供指示与斜坡电压组合的比较电压是否大于或小于像素电压的比较结果信号。 选择控制信号生成单元可以接收比较结果信号和模式控制信号，以指示粗略或精细模式，以提供允许修改粗略模式中的比较电压并且保持比较电压恒定的选择控制信号 精细模式。 参考电压选择单元可以接收选择控制信号以控制比较电压的修改。

公开(公告)号：US20120231593A1

公开(公告)日：2012-09-13

申请号：US13112767

申请日：2011-05-20

申请人： Han-Soo JOO ,  Sang-Hyun OH ,  Yu-Jin PARK

发明人： Han-Soo JOO ,  Sang-Hyun OH ,  Yu-Jin PARK

IPC分类号： H01L21/336

CPC分类号： H01L27/11556 ,  H01L27/1203

摘要： A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.

摘要翻译： 一种用于制造3D非易失性存储器件的方法，包括在衬底上形成子沟道，在衬底上形成堆叠层，所述堆叠层包括交替层叠有导电层的多个层间电介质层，选择性地蚀刻堆叠 以形成暴露子通道的第一开放区域，形成主通道导电层以间隙填充第一开放区域，选择性地蚀刻堆叠层和主沟道导电层以形成限定多个的第二开口区域 的主通道，并且形成隔离层以间隙填充第二开口区域。

公开(公告)号：US20120299087A1

公开(公告)日：2012-11-29

申请号：US13334017

申请日：2011-12-21

申请人： Han-Soo JOO ,  Yu-Jin PARK

发明人： Han-Soo JOO ,  Yu-Jin PARK

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

摘要： A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction.

摘要翻译： 非易失性存储器件包括栅极结构，其包括在衬底上交替层叠有控制栅极层的第一绝缘层，其中栅极结构沿第一方向延伸，沟道线分别在不同于第二方向的第二方向上延伸到栅极结构上 第一方向，形成在栅极结构和沟道线之间的存储层，并被布置成通过将栅极结构与沟道线电绝缘来捕获电荷，位线触点形成行，其各自沿第一方向延伸并接触第一方向的顶表面 通道线，源极线，其各自在第一方向上延伸并接触通道线的顶表面，其中源极线与位线接触行交替，并且位线位于位线上并且在第 第二个方向。