Abstract:
Disclosed herein are a display panel capable of improving operational reliability of a gate driver and a borderless type display including the same. The display panel allows light to be incident on at least one gate TFT of a gate driver formed to have a GIP structure to prevent degradation of gate TFTs due to positive shift of threshold voltage of the gate TFTs and to prevent reduction in output current of the gate driver, thereby improving the operational reliability of the gate driver.
Abstract:
A patterned retarder type 3D display includes a display panel including a plurality of unit pixels disposed in a matrix manner and a black matrix, a patterned retarder including a plurality of unit retarder patterns disposed at every row of the plurality of the unit pixels and located in front of the display panel, and a black strip including a main strip disposed as to be overlapped with the black matrix, the black strip being disposed between two unit pixels neighboring in a vertical direction and having a width expanded in any one direction of an upside direction and a down side direction from a border line of the unit retarder pattern, wherein outer lines of the black strips disposed at the each unit pixel are irregularly disposed, wherein the main strip extends in a horizontal direction.
Abstract:
An in-cell touch LCD device and a method of manufacturing the same are discussed. The in-cell touch LCD device may implement a screen display and a screen touch through a thin-film transistor substrate, which has an area larger than that of a color filter substrate, thus improving touch performance and ESD performance and simplifying a manufacturing process and reducing manufacturing costs.
Abstract:
Embodiments of the disclosure are related to display devices, a planarization layer disposed on a thin film transistor in a display panel is removed to form an opening in the planarization layer, and a top gate electrode is disposed in the opening of the planarization layer, thus a driving performance of the thin film transistor is enhanced while reducing a size of the thin film transistor disposed in the display panel. Furthermore, the top gate electrode is implemented using an electrode layer located on an upper layer of the planarization layer, the thin film transistor including double gate electrodes is implemented easily without an additional process.