公开(公告)号：US20230197003A1

公开(公告)日：2023-06-22

申请号：US17966347

申请日：2022-10-14

Applicant: LG Display Co., Ltd.

Inventor： Jin Her ,  Hoon Jeong ,  Chul Sang Shin

IPC: G09G3/3233 ,  G09G3/20

CPC classification number: G09G3/3233 ,  G09G3/2096 ,  G09G2300/0852 ,  G09G2300/0819 ,  G09G2310/0294 ,  G09G2330/021 ,  G09G2300/0828 ,  G09G2310/0286 ,  G09G2310/0289

Abstract: An electroluminescent display apparatus includes a plurality of pixels that each include a driving element including a first gate electrode connected to a first gate node, a second gate electrode facing the first gate electrode, a source electrode connected to a source node, and a drain electrode, a light emitting device connected between the source node and an input terminal for a low level driving voltage to emit light during an emission period, and an internal compensation circuit including a first capacitor connected to the first gate node and the source node. The internal compensation circuit samples a threshold voltage of the driving element during a sampling period that precedes the emission period. A sampling reinforcement voltage for increasing a sampling current flowing in the driving element is applied to the second gate electrode of the driving element during the sampling period.

公开(公告)号：US20250046250A1

公开(公告)日：2025-02-06

申请号：US18919834

申请日：2024-10-18

Applicant: LG Display Co., Ltd.

Inventor： Jin Her ,  Hoon Jeong ,  Chul Sang Shin

IPC: G09G3/3233 ,  G09G3/20

Abstract: An electroluminescent display apparatus includes a plurality of pixels that each include a driving element including a first gate electrode connected to a first gate node, a second gate electrode facing the first gate electrode, a source electrode connected to a source node, and a drain electrode, a light emitting device connected between the source node and an input terminal for a low level driving voltage to emit light during an emission period, and an internal compensation circuit including a first capacitor connected to the first gate node and the source node. The internal compensation circuit samples a threshold voltage of the driving element during a sampling period that precedes the emission period. A sampling reinforcement voltage for increasing a sampling current flowing in the driving element is applied to the second gate electrode of the driving element during the sampling period.

公开(公告)号：US12148377B2

公开(公告)日：2024-11-19

申请号：US17966347

申请日：2022-10-14

Applicant: LG Display Co., Ltd.

Inventor： Jin Her ,  Hoon Jeong ,  Chul Sang Shin

IPC: G09G3/3233 ,  G09G3/20

Abstract: An electroluminescent display apparatus includes a plurality of pixels that each include a driving element including a first gate electrode connected to a first gate node, a second gate electrode facing the first gate electrode, a source electrode connected to a source node, and a drain electrode, a light emitting device connected between the source node and an input terminal for a low level driving voltage to emit light during an emission period, and an internal compensation circuit including a first capacitor connected to the first gate node and the source node. The internal compensation circuit samples a threshold voltage of the driving element during a sampling period that precedes the emission period. A sampling reinforcement voltage for increasing a sampling current flowing in the driving element is applied to the second gate electrode of the driving element during the sampling period.

公开(公告)号：US11385515B2

公开(公告)日：2022-07-12

申请号：US17102208

申请日：2020-11-23

Applicant: LG Display Co., Ltd.

Inventor： Hoon Jeong ,  Chulsang Shin ,  Jin Her

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  H01L27/32 ,  H01L27/12

Abstract: Embodiments of the disclosure are related to display devices, a planarization layer disposed on a thin film transistor in a display panel is removed to form an opening in the planarization layer, and a top gate electrode is disposed in the opening of the planarization layer, thus a driving performance of the thin film transistor is enhanced while reducing a size of the thin film transistor disposed in the display panel. Furthermore, the top gate electrode is implemented using an electrode layer located on an upper layer of the planarization layer, the thin film transistor including double gate electrodes is implemented easily without an additional process.