公开(公告)号：US20160253976A1

公开(公告)日：2016-09-01

申请号：US14835631

申请日：2015-08-25

Applicant: LG Display Co., Ltd.

Inventor： Yong-Ho JANG ,  Woo-Seok CHOI

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

Abstract: Disclosed is a shift register capable of preventing charges supplied to a Q node to turn on a pull-up transistor for outputting a scan pulse from leaking outwards. The shift register includes a plurality of stages connected to gate lines formed at a panel. Each stage includes a scan signal generator for generating a scan pulse or a turn-off signal, a scan pulse controller for generating a Q-node control signal for generation of the scan pulse, a Q-node adjuster for preventing the Q-node control signal from leaking outwards during supply of the Q-node control signal to a Q-node connected to the scan signal generator, and a turn-off signal controller for transferring a Qb-node control signal for generation of the turn-off signal to the scan signal generator via a Qb-node when no scan pulse is generated from the scan signal generator.

Abstract translation: 公开了一种移位寄存器，其能够防止提供给Q节点的电荷导通用于输出扫描脉冲从外部泄漏的上拉晶体管。 移位寄存器包括连接到形成在面板上的栅极线的多个级。 每个级包括用于产生扫描脉冲或关断信号的扫描信号发生器，用于产生用于产生扫描脉冲的Q-节点控制信号的扫描脉冲控制器，用于防止Q-节点控制的Q-节点调节器 在将Q节点控制信号提供给连接到扫描信号发生器的Q节点时向外泄漏的信号，以及关闭信号控制器，用于将用于产生关断信号的Qb节点控制信号传送到 当扫描信号发生器没有产生扫描脉冲时，通过Qb节点扫描信号发生器。

公开(公告)号：US20140241488A1

公开(公告)日：2014-08-28

申请号：US14140776

申请日：2013-12-26

Applicant: LG DISPLAY CO., LTD.

Inventor： Yong-Ho JANG

IPC: G09G3/32 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3266 ,  G09G2310/0286

Abstract: A shift register includes a plurality of stages each outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node. The voltage at the at least one A-reset node and any one A-clock pulse, at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

Abstract translation: 移位寄存器包括多个级，每个级输出包括A扫描脉冲和B扫描脉冲的k个复合脉冲。 至少一级包括用于响应于外部A控制信号控制A组节点处的电压和至少一个A复位节点处的电压的A子级，并且基于 A组节点处的电压。 在至少一个A复位节点处的电压和任何一个A时钟脉冲，至少一个用于控制B组节点处的电压的B级和响应中的至少一个B复位节点处的电压 一个外部B控制信号并产生一个B进位脉冲;一个扫描输出控制器，用于产生k个A扫描脉冲和k个B扫描脉冲，并输出一个A扫描脉冲和一个B扫描脉冲 对应于一个复合脉冲。

公开(公告)号：US20170004760A1

公开(公告)日：2017-01-05

申请号：US15186107

申请日：2016-06-17

Applicant: LG Display Co., Ltd.

Inventor： Yong-Ho JANG ,  Woo-Seok CHOI

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G02F1/1345 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0223 ,  G11C19/28

Abstract: Discussed are a built-in gate driver capable of improving output characteristics of the gate driver by reducing load of clock lines and a display device using the same. The built-in gate driver can include a shift register, a first clock group and a second clock group located in a non-display region of a display panel. The shift register includes a plurality of stages for individually driving gate lines of a display region. The first clock group includes clock lines arranged at a first side of the shift register. The second clock group includes clock lines arranged at a second side of the shift register. Each of the clock lines includes a main line and a branch line branched from the main line and connected to a corresponding stage. A branch line belonging to a corresponding clock group of any one of the first and second clock groups does not overlap a main line belonging to the other clock group.

Abstract translation: 讨论的是内置栅极驱动器，能够通过减少时钟线的负载和使用其的显示装置来改善栅极驱动器的输出特性。 内置栅极驱动器可以包括位于显示面板的非显示区域中的移位寄存器，第一时钟组和第二时钟组。 移位寄存器包括用于单独驱动显示区域的栅极线的多个级。 第一时钟组包括布置在移位寄存器第一侧的时钟线。 第二时钟组包括布置在移位寄存器第二侧的时钟线。 每个时钟线包括主线和从主线分支并连接到相应的一个分支线。 属于第一和第二时钟组中的任何一个的对应时钟组的分支线不与属于另一个时钟组的主线重叠。

公开(公告)号：US20160322116A1

公开(公告)日：2016-11-03

申请号：US15140931

申请日：2016-04-28

Applicant: LG Display Co., Ltd.

Inventor： Yong-Ho JANG ,  Jong-Uk BAE

IPC: G11C19/28 ,  G09G3/20 ,  H01L29/786

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/028 ,  G11C19/287 ,  H01L29/7869

Abstract: Disclosed is a shift register which prevents current leakage and degradation of an oxide transistor due to light to improve output stability, and a display device using the same. The shift register includes a plurality of stages, and each stage includes a transmission line unit including a plurality of clock lines to supply a plurality of clock signals and a plurality of power lines to supply a plurality of voltages, a transistor unit including a plurality of transistors, and a light-shielding layer overlapping at least one transistor of the transistor unit so as to block light.

Abstract translation: 公开了一种移位寄存器，其防止由于光引起的氧化物晶体管的电流泄漏和劣化以提高输出稳定性，以及使用该移位寄存器的显示装置。 移位寄存器包括多个级，并且每个级包括传输线单元，其包括提供多个时钟信号的多个时钟线和多个电源线以提供多个电压;晶体管单元，包括多个 晶体管，以及与晶体管单元的至少一个晶体管重叠的遮光层，以阻挡光。

公开(公告)号：US20150317954A1

公开(公告)日：2015-11-05

申请号：US14701097

申请日：2015-04-30

Applicant: LG Display Co., Ltd.

Inventor： Yong-Ho JANG

IPC: G09G5/18 ,  G09G3/34 ,  G09G3/32 ,  G11C19/28 ,  G09G3/36

Abstract: A shift register capable of preventing leakage current and a display device using the same are disclosed. The shift register includes a plurality of stages. Each stage includes a set unit setting a Q node in response to a start pulse or previous output, an inverter for controlling a QB node to have a logic state opposite to that of the Q node, an output unit for outputting any one input clock or a gate off voltage in response to the logic states of the Q and QB nodes, a reset unit including a reset switching element, the reset switching element resetting the Q node with a first reset voltage in response to a reset pulse or next output, and a noise cleaner resetting the Q node with a second reset voltage in response to the QB node. When the reset switching element is turned off, the first reset voltage is greater than a voltage of the reset pulse or the next output for the current.

Abstract translation: 公开了能够防止泄漏电流的移位寄存器和使用该移位寄存器的显示装置。 移位寄存器包括多个级。 每个级包括响应于起始脉冲或先前输出设置Q节点的设置单元，用于控制QB节点具有与Q节点相反的逻辑状态的反相器，用于输出任何一个输入时钟的输出单元或 响应于所述Q和QB节点的逻辑状态的门关断电压，包括复位开关元件的复位单元，所述复位开关元件响应于复位脉冲或下一个输出以第一复位电压复位所述Q节点;以及 噪声清除器响应于QB节点以第二复位电压重置Q节点。 当复位开关元件关闭时，第一复位电压大于复位脉冲的电压或电流的下一个输出。

公开(公告)号：US20140185737A1

公开(公告)日：2014-07-03

申请号：US14135369

申请日：2013-12-19

Applicant: LG DISPLAY CO., LTD.

Inventor： Yong-Ho JANG

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3266 ,  G09G2310/0286

Abstract: A shift register includes a plurality of stages each for outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-sub-stages each for controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

Abstract translation: 移位寄存器包括多个级，用于输出每个包括A扫描脉冲和B扫描脉冲的k个复合脉冲。 至少一个级包括响应于外部A控制信号而分别用于控制A组节点处的电压和电压至少一个A复位节点的k个A级，并且基于 A组节点处的电压，至少一个A复位节点处的电压和任何一个A时钟脉冲，用于控制B组节点处的电压的B子级和至少一个电压 B复位节点，并产生B进位脉冲;以及扫描输出控制器，用于产生k个A扫描脉冲和k个B扫描脉冲，并输出一个A扫描脉冲和一个A扫描脉冲 的B扫描脉冲作为一个复合脉冲。

公开(公告)号：US20130322593A1

公开(公告)日：2013-12-05

申请号：US13960534

申请日：2013-08-06

Applicant: LG DISPLAY CO., LTD.

Inventor： Yong-Ho JANG ,  Seung-Chan CHOI

IPC: G11C19/00

CPC classification number: G11C19/00 ,  G11C19/28

Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.

Abstract translation: 这里讨论的是能够稳定其输出的移位寄存器。 移位寄存器包括多个级，用于顺序地输出扫描脉冲，使得扫描脉冲的高持续时间彼此部分重叠。 每个级包括用于控制设定节点的充电持续时间的节点控制器，以及用于通过输出端输出对应的一个扫描脉冲以用于设定节点的充电持续时间的输出单元。