Abstract:
A display device is provided that includes a display panel divided into a plurality of blocks, each of the blocks including a plurality of lines of pixels and configured to be driven in a time-division manner with a touch sensing period interposed between two display periods, the two display periods corresponding to display periods for two adjacent blocks of the plurality of blocks. The display device further includes a display driving circuit, and a touch sensing unit configured to receive a sync signal for synchronizing the display driving circuit with the touch sensing unit. The display device is configured to change the sync signal every predetermined period of time so as to shift the touch sensing period interposed between the two display periods.
Abstract:
Provided are a display device, a scan driver, and a method of manufacturing the same. A scan driver includes: a level shifter configured to output a power and a signal, and a scan signal generating circuit configured to generate a scan signal based on the power and the signal supplied from the level shifter, the scan signal generating circuit including a buffer configured to transmit a clock signal to a stage of a shift register, the buffer including two inverters, one of the two inverters being included in a multi-buffer.
Abstract:
The disclosure relates to data driver and organic light emitting display device. The data driver includes: an input unit configured to receive an input data; a compensation data generator configured to generate a compensation data by applying a compensation value to the input data; a converter unit configured to convert the input data into an image data voltage and to convert the compensation data into a compensation data voltage; and an output unit configured to separately output the image data voltage and the compensation data voltage to a data line of the organic light emitting display.
Abstract:
A display device and a gate driver circuit of the display device are disclosed. The display device includes a shift register that shifts a gate pulse in accordance with a shift clock and sequentially supplies the gate pulse to gate lines. At least one stage of the shift register includes a discharge blocking node connected to a source terminal of the second transistor, and a discharge blocking circuit configured to charge the discharge blocking node when the Q node is charged, and discharge the discharge blocking node when the Q node is discharged.