公开(公告)号：US10651256B2

公开(公告)日：2020-05-12

申请号：US15957139

申请日：2018-04-19

Applicant: LG Display Co., Ltd.

Inventor： Kummi Oh ,  Hyeseon Eom ,  Shunyoung Yang ,  Jeoungin Lee

IPC: H01L27/32 ,  H01L27/12 ,  H01L51/52 ,  H01L51/56

Abstract: Provided are a thin film transistor (TFT) substrate and a method of manufacturing the same. A TFT substrate includes: a substrate defining a pixel area, a first TFT including: an oxide semiconductor layer, a first gate electrode on the oxide semiconductor layer, a first source electrode, and a first drain electrode, a second TFT including: a second gate electrode, a polycrystalline semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a first gate insulating layer under the first gate electrode and the second gate electrode, the first gate insulating layer covering the oxide semiconductor layer, a second gate insulating layer under the polycrystalline semiconductor layer, the second gate insulating layer covering the first gate electrode and the second gate electrode, and an intermediate insulating layer on the first gate electrode and the polycrystalline semiconductor layer, the intermediate insulating layer including a nitride layer.

公开(公告)号：US09997579B2

公开(公告)日：2018-06-12

申请号：US15359922

申请日：2016-11-23

Applicant: LG Display Co., Ltd.

Inventor： Kummi Oh ,  Hyeseon Eom ,  Shunyoung Yang ,  Jeoungin Lee

IPC: H01L29/08 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

CPC classification number: H01L27/3262 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/3246 ,  H01L27/3248 ,  H01L51/5206 ,  H01L51/5221 ,  H01L51/56

Abstract: Provided are a thin film transistor (TFT) substrate and a method of manufacturing the same. A TFT substrate includes: a substrate defining a pixel area, a first TFT including: an oxide semiconductor layer, a first gate electrode on the oxide semiconductor layer, a first source electrode, and a first drain electrode, a second TFT including: a second gate electrode, a polycrystalline semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a first gate insulating layer under the first gate electrode and the second gate electrode, the first gate insulating layer covering the oxide semiconductor layer, a second gate insulating layer under the polycrystalline semiconductor layer, the second gate insulating layer covering the first gate electrode and the second gate electrode, and an intermediate insulating layer on the first gate electrode and the polycrystalline semiconductor layer, the intermediate insulating layer including a nitride layer.