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公开(公告)号:US10332467B2
公开(公告)日:2019-06-25
申请号:US15125468
申请日:2015-03-10
Applicant: LG DISPLAY CO., LTD.
Inventor: Bo Sun Lee , Hun Jeoung , Sang Hee Yu , Sung Hyun Cho , Sung Wook Chang
IPC: G09G3/3266 , G09G3/36 , G11C19/28 , G06F3/041 , G09G3/20
Abstract: Present invention relates to a display device and a driving method thereof. In particular, the present invention is to provide a display device and a driving method thereof, which block at least one of scan signals output from gate lines according to an enable signal.
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公开(公告)号:US20230298530A1
公开(公告)日:2023-09-21
申请号:US18200463
申请日:2023-05-22
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/043
Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.
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公开(公告)号:US12131705B2
公开(公告)日:2024-10-29
申请号:US18200463
申请日:2023-05-22
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang
IPC: G09G3/3233 , G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/043
Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.
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公开(公告)号:US20220366855A1
公开(公告)日:2022-11-17
申请号:US17742011
申请日:2022-05-11
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang
IPC: G09G3/3266
Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.
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公开(公告)号:US10338727B2
公开(公告)日:2019-07-02
申请号:US15261796
申请日:2016-09-09
Applicant: LG Display Co., Ltd.
Inventor: Sang Hee Yu , Hun Jeoung , Sung Hyun Cho , Bo Sun Lee , Sung Wook Chang
Abstract: Present invention is related to a display device and a driving method thereof, and particularly, to a display device and a driving method thereof, which control an output timing of a scan signal output to gate lines by using two or more external start signals having different timings.
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公开(公告)号:US09997112B2
公开(公告)日:2018-06-12
申请号:US15124954
申请日:2015-03-10
Applicant: LG DISPLAY CO., LTD.
Inventor: Hun Jeoung , Sang Hee Yu , Sung Hyun Cho , Bo Sun Lee , Sung Wook Chang
IPC: G09G3/3266 , G09G3/36 , G11C19/28 , G09G3/3258 , G09G3/3291 , G11C19/00 , G09G3/20 , G09G3/32
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/32 , G09G3/3258 , G09G3/3291 , G09G3/3614 , G09G3/3677 , G09G3/3688 , G09G3/3696 , G09G2310/02 , G09G2310/021 , G09G2310/0213 , G09G2310/0224 , G09G2310/0286 , G09G2310/0291 , G09G2310/04 , G09G2340/0435 , G11C19/00 , G11C19/28
Abstract: Present invention is related to a display device and a driving method thereof. In particularly, the present invention is to provide a display device and a driving method thereof, in which a data driver driven at a low frequency which is capable of inverting a polarity of a data voltage in each frame.
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公开(公告)号:US12190819B2
公开(公告)日:2025-01-07
申请号:US17588982
申请日:2022-01-31
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang
IPC: G09G3/3258 , G09G3/3266 , G09G3/3291
Abstract: A pixel driving circuit in each of the pixels includes: a first switching circuit that turned on in response to the (n-2) th scan signal to provide a V1 voltage to a first node, provide a V3 voltage to a third node, and provide a V2 voltage to an anode of the light-emitting element; a second switching circuit turned on in response to the nth scan signal to electrically connect the first node to a second node, provide a V5 voltage to the third node, and provide a data voltage to a fourth node; and an emission control circuit turned on in response to the nth emission signal to electrically connect a second node to the anode and provide a reference voltage to the fourth node.
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公开(公告)号:US11694629B2
公开(公告)日:2023-07-04
申请号:US17742011
申请日:2022-05-11
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/043
Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.
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公开(公告)号:US11270644B2
公开(公告)日:2022-03-08
申请号:US17107875
申请日:2020-11-30
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang
IPC: G06F3/038 , G09G5/00 , G09G3/3258 , G09G3/3291 , G09G3/3266
Abstract: A pixel driving circuit in each of the pixels includes: a first switching circuit that is turned on in response to the (n−2)th scan signal to provide a V1 voltage to a first node, provide a V3 voltage to a third node, and provide a V2 voltage to an anode of the light-emitting element; a second switching circuit turned on in response to the nth scan signal to electrically connect the first node to a second node, provide a V5 voltage to the third node, and provide a data voltage to a fourth node; and an emission control circuit turned on in response to the nth emission signal to electrically connect a second node to the anode and provide a reference voltage to the fourth node.
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公开(公告)号:US10424266B2
公开(公告)日:2019-09-24
申请号:US15603024
申请日:2017-05-23
Applicant: LG Display Co., Ltd.
Inventor: Sung Wook Chang , Se Wan Lee
IPC: G11C19/00 , G09G3/36 , G09G3/20 , G11C19/28 , G09G3/3266
Abstract: Provided are a gate driving circuit and a display device using the same. The gate driving circuit includes a shift register including a plurality of stages. A stage of the stages includes a first transistor configured to charge a first node with a first voltage level of a high voltage terminal of the stage. The first voltage level is higher than a second voltage level of a low voltage terminal of the stage. The stage further includes a control circuit connected to the first transistor. The control circuit is connected to the high voltage terminal and to an output terminal of a previous stage of the shift register. The control circuit is configured to control the first transistor to increase a voltage of the first node to be higher than a third voltage level, which is less than the first voltage level by a threshold voltage of the first transistor.
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