Gate Driver and Electroluminescent Display Apparatus Including the Same

    公开(公告)号:US20230298530A1

    公开(公告)日:2023-09-21

    申请号:US18200463

    申请日:2023-05-22

    Inventor: Sung Wook Chang

    CPC classification number: G09G3/3266 G09G2300/043

    Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.

    Gate driver and electroluminescent display apparatus including the same

    公开(公告)号:US12131705B2

    公开(公告)日:2024-10-29

    申请号:US18200463

    申请日:2023-05-22

    Inventor: Sung Wook Chang

    CPC classification number: G09G3/3266 G09G2300/043

    Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.

    Gate Driver and Electroluminescent Display Apparatus Including the Same

    公开(公告)号:US20220366855A1

    公开(公告)日:2022-11-17

    申请号:US17742011

    申请日:2022-05-11

    Inventor: Sung Wook Chang

    Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.

    Pixel driving circuit and electroluminescent display device including the same

    公开(公告)号:US12190819B2

    公开(公告)日:2025-01-07

    申请号:US17588982

    申请日:2022-01-31

    Inventor: Sung Wook Chang

    Abstract: A pixel driving circuit in each of the pixels includes: a first switching circuit that turned on in response to the (n-2) th scan signal to provide a V1 voltage to a first node, provide a V3 voltage to a third node, and provide a V2 voltage to an anode of the light-emitting element; a second switching circuit turned on in response to the nth scan signal to electrically connect the first node to a second node, provide a V5 voltage to the third node, and provide a data voltage to a fourth node; and an emission control circuit turned on in response to the nth emission signal to electrically connect a second node to the anode and provide a reference voltage to the fourth node.

    Gate driver and electroluminescent display apparatus including the same

    公开(公告)号:US11694629B2

    公开(公告)日:2023-07-04

    申请号:US17742011

    申请日:2022-05-11

    Inventor: Sung Wook Chang

    CPC classification number: G09G3/3266 G09G2300/043

    Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.

    Pixel driving circuit and electroluminescent display device including the same

    公开(公告)号:US11270644B2

    公开(公告)日:2022-03-08

    申请号:US17107875

    申请日:2020-11-30

    Inventor: Sung Wook Chang

    Abstract: A pixel driving circuit in each of the pixels includes: a first switching circuit that is turned on in response to the (n−2)th scan signal to provide a V1 voltage to a first node, provide a V3 voltage to a third node, and provide a V2 voltage to an anode of the light-emitting element; a second switching circuit turned on in response to the nth scan signal to electrically connect the first node to a second node, provide a V5 voltage to the third node, and provide a data voltage to a fourth node; and an emission control circuit turned on in response to the nth emission signal to electrically connect a second node to the anode and provide a reference voltage to the fourth node.

    Gate driving circuit and display device using the same

    公开(公告)号:US10424266B2

    公开(公告)日:2019-09-24

    申请号:US15603024

    申请日:2017-05-23

    Abstract: Provided are a gate driving circuit and a display device using the same. The gate driving circuit includes a shift register including a plurality of stages. A stage of the stages includes a first transistor configured to charge a first node with a first voltage level of a high voltage terminal of the stage. The first voltage level is higher than a second voltage level of a low voltage terminal of the stage. The stage further includes a control circuit connected to the first transistor. The control circuit is connected to the high voltage terminal and to an output terminal of a previous stage of the shift register. The control circuit is configured to control the first transistor to increase a voltage of the first node to be higher than a third voltage level, which is less than the first voltage level by a threshold voltage of the first transistor.

Patent Agency Ranking